NS16C2552 Datasheet PDF - National Semiconductor
|(NS16C2552 / NS16C2752) Dual UART
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Dual UART with 16-byte/64-byte FIFO’s and up to
5 Mbit/s Data Rate
1.0 General Description
The NS16C2552 and NS16C2752 are dual channel Univer-
sal Asynchronous Receiver/Transmitter (DUART). The foot-
print and the functions are compatible to the PC16552D,
while new features are added to the UART device. These
features include low voltage support, 5V tolerant inputs,
enhanced features, enhanced register set, and higher data
The two serial channels are completely independent of each
other, except for a common CPU interface and crystal input.
On power-up both channels are functionally identical to the
PC16552D. Each channel can operate with on-chip transmit-
ter and receiver FIFO’s (in FIFO mode).
In the FIFO mode each channel is capable of buffering 16
bytes (for NS16C2552) or 64 bytes (for NS16C2752) of data
in both the transmitter and receiver. The receiver FIFO also
has additional 3 bits of error data per location. All FIFO
control logic is on-chip to minimize system software over-
head and maximize system efficiency.
To improve the CPU processing bandwidth, the data trans-
fers between the DUART and the CPU can be done using
DMA controller. Signaling for DMA transfers is done through
two pins per channel (TXRDY and RXRDY). The RXRDY
function is multiplexed on one pin with the OUT2 and BAUD-
OUT functions. The configuration is through Alternate Func-
The fundamental function of the UART is converting be-
tween parallel and serial data. Serial-to-parallel conversion
is done on the UART receiver and parallel-to-serial conver-
sion is done on the transmitter. The CPU can read the
complete status of each channel at any time. Status infor-
mation reported includes the type and condition of the trans-
fer operations being performed by the DUART, as well as
any error conditions (parity, overrun, framing, or break inter-
The NS16C2552 and NS16C2752 include one program-
mable baud rate generator for each channel. Each baud rate
generator is capable of dividing the clock input by divisors of
1 to (216 - 1), and producing a 16X clock for driving the
internal transmitter logic and for receiver sampling circuitry.
The NS16C2552 and NS16C2752 have complete MODEM-
control capability, and a processor-interrupt system. The
interrupts can be programmed by the user to minimize the
processing required to handle the communications link.
n Dual independent UART
n Up to 5 Mbits/s data transfer rate
n 2.97 V to 5.50 V operational Vcc
n 5 V tolerant I/Os in the entire supply voltage range
n Industrial Temperature: -40˚C to 85˚C
n Default registers are identical to the PC16552D
n NS16C2552/NS16C2752 is pin-to-pin compatible to
NSC PC16552D, EXAR ST16C2552, XR16C2552, XR
16L2552, and Phillips SC16C2552B
n NS16C2752 is compatible to EXAR XR16L2752, and
register compatible to Phillips SC16C752
n Auto Hardware Flow Control (Auto-CTS, Auto-RTS)
n Auto Software Flow Control (Xon, Xoff, and Xon-any)
n Fully programmable character length (5, 6, 7, or 8) with
even, odd, or no parity, stop bit
n Adds or deletes standard asynchronous communication
bits (start, stop, and parity) to or from the serial data
n Independently controlled and prioritized transmit and
n Complete line status reporting capabilities
n Line break generation and detection
n Internal diagnostic capabilities
— Loopback controls for communications link fault
— Break, parity, overrun, framing error detection
n Programmable baud generators divide any input clock
by 1 to (216 - 1) and generate the 16 X clock
n IrDA v1.0 wireless Infrared encoder/decoder
n DMA operation (TXRDY/RXRDY)
n Concurrent write to DUART internal register channels 1
n Multi-function output allows more package functions with
fewer I/O pins
n 44-PLCC or 48-TQFP package
© 2006 National Semiconductor Corporation DS202048
5.0 Pin Descriptions
The NS16C2552/NS16C2752 pins are classified into the
following interface categories.
• Bus Interface
• Serial I/O Interface
• Clock and Reset
• Power supply and Ground pins
Serial channel number (1 or 2) is designated by a numerical
suffix after each pin name. If a numerical suffix (1 or 2) is not
associated with the pin name, the information applies to both
5.1 PARALLEL BUS INTERFACE
The I/O types are as follows:
Data bus comprises eight TRI-STATE input/output lines. The bus provides
bidirectional communications between the UART and the CPU. Data, control words,
and status information are transferred via the D7-D0 Data Bus.
Address signals connected to these 3 inputs select a DUART register for the CPU to
read from or write to during data transfer. Table 1 shows the registers and their
addresses. Note that the state of the Divisor Latch Access Bit (DLAB), which is the
most significant bit of the Line Control Register, affects the selection of certain
DUART registers. The DLAB must be set high by the system software to access the
Baud Generator Divisor Latches and the Alternate Function Register.
When CS is low, the chip is selected. This enables communication between the
DUART and the CPU. Valid chip select should stabilize according to the tAW
CHSL directs the address and data information to the selected serial channel. (Table
1 = channel 1 is selected.
0 = channel 2 is selected.
The register data is placed on the D0 - D7 on the falling edge of RD. The CPU can
read status information or data from the selected DUART register on the rising edge.
On the falling edge of WR, data is placed on the D0 - D7. On the rising edge, the data
is latched into the selected DUART register.
UART Receive-ready: The receiver DMA signaling is available through this pin which
is a seperate pin on the TQFP package, while on the PLCC package it is available
through the MF pins (19, 35). When operating in the FIFO mode, the CPU selects
one of two types of DMA transfer via FCR. When operating in the 16450 Mode,
only DMA mode 0 is available. Mode 0 supports single transfer DMA (and a transfer is
usually made between CPU bus cycles). Mode 1 supports multi-transfer DMA where
multiple transfers are made continuously until the Rx FIFO is empty. Details regarding
the active and inactive states of this signal are described in Section 6.5 FIFO
CONTROL REGISTER (FCR) and Section 7.9 DMA OPERATION.
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