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What is ISL23711?

This electronic component, produced by the manufacturer "Intersil Corporation", performs the same function as "Taps IC Serial Interface".


ISL23711 Datasheet PDF - Intersil Corporation

Part Number ISL23711
Description Taps IC Serial Interface
Manufacturers Intersil Corporation 
Logo Intersil Corporation Logo 


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ISL23711
®
Volatile Digitally Controlled Potentiometer (XDCP™)
Data Sheet
August 16, 2005
FN6127.0
Terminal Voltage ±3V or ±5V, 128 Taps I2C
Serial Interface
The Intersil ISL23711 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, and a control section. The wiper position is
controlled by an I2C interface.
The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. The wiper terminal can be connected to either end
of the resistor array or at any one of the Tap Positions in
between, providing 128 steps of resolution between RL and
RH. The “position” of the wiper is determined by the value
assigned to the volatile Wiper Register (WR). The WR can
be directly written to and read from using standard I2C
interface protocol. The device is available in either a 10kor
50kversion.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
• Industrial and Automotive Control
• Parameter and Bias Adjustments
• Amplifier Bias and Control
Ordering Information
PART NUMBER
(BRAND)
RESISTANCE
OPTION ()
TEMP
RANGE
(°C)
PKG.
PACKAGE DWG. #
ISL23711WIU10Z
10K -40 to +85 10 Ld MSOP M10.118
(AOE) (Notes 1, 2)
(Pb-Free)
ISL23711UIU10Z
50K -40 to +85 10 Ld MSOP M10.118
(AOD) (Notes 1, 2)
(Pb-Free)
NOTES:
1. Add “-T” suffix for tape and reel.
2. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• I2C Serial Interface with Hardwire Slave Address Allows
up to Four Devices
• DCP Terminal Voltage, from V- to VCC
• 127 Resistive Elements
- Typical RTOTAL tempco ±50ppm/°C
- Typical ratiometric tempco ±4ppm/°C
- End to end resistance range ±20%
- Wiper resistance = 70typ at VCC = 3.3V
• Low Power CMOS
- Standby current, 500nA max
- Active current, 200µA max
- VCC = 2.7V to 5.5V
- V- = -2.7V to -5.5V
• RTOTAL Values = 10kΩ, 50k
• Volatile Wiper Storage
• Package
- 10 Ld MSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL23711
(10 LD MSOP)
TOP VIEW
SDA
V-
GND
A1
A0
1
2
3
4
5
10 SCL
9 VCC
8 RL
7 RW
6 RH
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL23711 equivalent
ISL23711
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 1)
tDH Output Data Hold Time
tR SDA, SCL, A0, A1 Rise Time
(Note 14)
From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window
From 30% to 70% of VCC
0
20 +
0.1 * Cb
tF SDA, SCL, A0, A1 Fall Time
(Note 14)
From 70% to 30% of VCC
20 +
0.1 * Cb
Cb Capacitive Loading of SDA or SCL
(Note 14)
Total on-chip and off-chip
10
Rpu SDA and SCL Bus Pull-up Resistor
(Note 14) Off-chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1
tSU:A
tHD:A
A0, A1 Setup Time
A0, A1 Hold Time
Before START condition
After STOP condition
600
600
MAX
250
250
400
SDA vs SCL Timing
UNIT
ns
ns
ns
pF
k
ns
ns
SCL
tSU:STA
SDA
(INPUT TIMING)
tF tHIGH
tSU:DAT
tHD:STA
SDA
(OUTPUT TIMING)
A0, A1 Pin Timing
START
SCL
Clk 1
tLOW
tR
tHD:DAT
tAA tDH
STOP
tSU:STO
tBUF
SDA IN
A0, A1
tSU:A
tHD:A
5 FN6127.0
August 16, 2005


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