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What is IDT72V3673?

This electronic component, produced by the manufacturer "IDT", performs the same function as "(IDT72V36x3) 3.3 VOLT CMOS SyncFIFOTM".


IDT72V3673 Datasheet PDF - IDT

Part Number IDT72V3673
Description (IDT72V36x3) 3.3 VOLT CMOS SyncFIFOTM
Manufacturers IDT 
Logo IDT Logo 


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3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36
4,096 x 36
8,192 x 36
IDT72V3653
IDT72V3663
IDT72V3673
FEATURES
Memory storage capacity:
IDT72V3653 – 2,048 x 36
IDT72V3663 – 4,096 x 36
IDT72V3673 – 8,192 x 36
Clock frequencies up to 100 MHz (6.5 ns access time)
Clocked FIFO buffering data from Port A to Port B
IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Retransmit Capability
Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of the 5V operating
IDT723653/723663/723673
Pin compatible with the lower density parts, IDT72V3623/
72V3633/72V3643
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RS1
RS2
PRS
RT
RTM
FIFO1
Mail1,
Mail2,
Reset
Logic
36
FIFO
Retransmit
Logic
A0-A35
Mail 1
Register
36
RAM ARRAY
2,048 x 36
36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
MBF1
36
B0-B35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
FS2
FS0/SD
FS1/SEN
36
Programmable Flag
Timing
Offset Registers
Mode
13
MBF2
Mail 2
Register
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFOis a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
36
Port-B
Control
Logic
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4662 drw01
NOVEMBER 2003
DSC-4662/2

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IDT72V3673 equivalent
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
MBA
MBB
Name
Port A Mailbox
Select
Port B Mailbox
Select
MBF1
Mail1 Register Flag
MBF2
Mail2 Register Flag
RS1, RS2 Resets
PRS/ PartialReset/
RT Retransmit
RTM
SIZE(1)
W/RA
W/RB
Retransmit Mode
Bus Size Select
(Port B)
Port A Write/
Read Select
Port B Write/
Read Select
I/O Description
I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and
a LOW level selects FIFO data for output.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH
following either a Reset (RS1) or Partial Reset (PRS).
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-
HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH
following either a Reset (RS2) or Partial Reset (PRS).
I A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and
setsthePortBoutputregistertoallzeroes. ALOW-to-HIGHtransition on RS1 selects the programming
method (serial or parallel) and one of five programmable flag default offsets. It also configures Port
B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while RS1 is LOW.
I ThispinmuxedforbothPartialResetandRetransmitoperations,itisusedinconjunctionwiththeRTM
pin. If RTM is LOW, then a LOW on this pin initializes the FIFO read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently
selectedbussize,endian arrangement,programmingmethod(serialorparallel),andprogrammable
flag settings are all retained. If RTM is HIGH, then a LOW on this pin performs a Retransmit and initializes
the read pointer only, to the first memory location.
I This pin is used in conjunction with the RT pin. When RTM is HIGH a Retransmit is performed when
RT is taken HIGH.
I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size
and endian arrangement for Port B. The level of SIZE must be static throughout device operation.
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
NOTE:
1. FS2, BM and Size inputs are not TTL compatible. These inputs should be tied to GND or VCC.
5


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