What is FM20L08?

This electronic component, produced by the manufacturer "Ramtron", performs the same function as "1Mbit Bytewide FRAM Memory".

FM20L08 Datasheet PDF - Ramtron

Part Number FM20L08
Description 1Mbit Bytewide FRAM Memory
Manufacturers Ramtron 
Logo Ramtron Logo 

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1Mbit Bytewide FRAM Memory – Extended Temp.
1Mbit Ferroelectric Nonvolatile RAM
Organized as 128Kx8
Unlimited Read/Write Cycles
NoDelay™ Writes
Page Mode Operation to 33MHz
Advanced High-Reliability Ferroelectric Process
SRAM Replacement
JEDEC 128Kx8 SRAM pinout
60 ns Access Time, 350 ns Cycle Time
System Supervisor
Low Voltage monitor drives external /LVL signal
Write protects memory for low voltage condition
Software programmable block write protect
The FM20L08 is a 128K x 8 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or FRAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and unlimited write endurance make
FRAM superior to other types of memory.
In-system operation of the FM20L08 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The FRAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM20L08 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in the form of an SRAM.
The FM20L08 includes a voltage monitor function
that monitors the power supply voltage. It asserts an
active-low signal that indicates the memory is write-
protected when VDD drops below a critical threshold.
When the /LVL signal is low, the memory is
protected against an inadvertent access and data
Superior to Battery-backed SRAM Modules
No battery concerns
Monolithic reliability
True surface mount solution, no rework steps
Superior for moisture, shock, and vibration
Resistant to negative voltage undershoots
Low Power Operation
3.3V +10%, -5% Power Supply
22 mA Active Current
Industry Standard Configurations
Extended Temperature -25° C to +85° C
32-pin “green” TSOP (-TG)
The FM20L08 also features software-controlled write
protection. The memory array is divided into 8
uniform blocks, each of which can be individually
write protected.
Device specifications are guaranteed over the
temperature range -25°C to +85°C.
Pin Configuration
32 OE
31 A10
30 CE
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 VSS
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
Ordering Information
FM20L08-60-TG 60 ns access, 32-pin
“Green” TSOP
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.4
Oct. 2005
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Page 1 of 14

FM20L08 equivalent
Supply Voltage Monitor
An internal voltage monitor circuit continuously
checks the VDD supply voltage. When VDD is below
the specified threshold VTP, the monitor asserts the
/LVL signal to an active-low state. The FM20L08
locks out access to the memory when VDD is below
the trip voltage. This prevents the system from
accessing memory when VDD is too low and
inadvertently corrupting the data. The /LVL signal
should not be used as a system reset signal because
the system host may attempt to write data to the
FM20L08 below its specified operating voltage. The
/LVL pin may be used as a status indicator that the
memory is locked out.
On power up, the /LVL signal will begin in a low
state signifying that VDD is below the VTP threshold. It
will remain low as long as VDD is below that level.
Once VDD rises above VTP, a hold-off timer will begin
creating the delay tPULV. Once this delay has elapsed,
the /LVL signal will go high or inactive. At this time
the memory can be accessed. The memory is ready
for access prior to tPU as shown in the Electrical
Specifications section. The /LVL signal will remain
high until VDD drops below the threshold.
Software Write Protection
The 128Kx8 address space is divided into 8 sectors
(blocks) of 16Kx8 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands and two write commands.
The specific sequence of read addresses must be
provided in order to access to the write protect mode.
Following the read address sequence, the host must
write a data byte that specifies the desired protection
state of each sector. For confirmation, the system
must then write the complement of the protection byte
immediately following the protection byte. Any error
that occurs including read addresses in the wrong
order, issuing a seventh read address, or failing to
complement the protection value will leave the write
protection unchanged.
The write-protect state machine monitors all
addresses, taking no action until the write-protect
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
FM20L08 - Extended Temp.
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
write address is ignored. Rather the byte will be held
pending the next cycle, which must be a write of the
data complement to the protection settings. If the
complement is correct, the write protect settings will
be updated. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six addresses will not be entered into
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector.
Setting a bit to 1 write protects the corresponding
sector; a 0 enables writes for that sector. The
following table shows the write-protect sectors with
the corresponding bit that controls the write-protect
Write Protect Sectors – 16K x8 blocks
Sector 7
1FFFFh – 1C000h
Sector 6
1BFFFh – 18000h
Sector 5
17FFFh – 14000h
Sector 4
13FFFh – 10000h
Sector 3
0FFFFh – 0C000h
Sector 2
0BFFFh – 08000h
Sector 1
07FFFh – 04000h
Sector 0
03FFFh – 00000h
The write-protect address sequence follows:
1. 05555h *
2. 1AAAAh
3. 03333h
4. 1CCCCh
5. 100FFh
6. 0FF00h
7. 1AAAAh
8. 1CCCCh
9. 0FF00h
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 05555h.
The address sequence provides a very secure way of
modifying the protection. The correct address
sequence has a 1 in 5 x 1030 chance of occurring
accidentally. A flow chart of the entire write protect
operation is shown in Figure 2. As mentioned above,
write-protect settings are nonvolatile. The factory
default is unprotected.
Rev. 1.4
Oct. 2005
Page 5 of 14


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Part Details

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