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What is AN-686?

This electronic component, produced by the manufacturer "Analog Devices", performs the same function as "APPLICATION NOTE".


AN-686 Datasheet PDF - Analog Devices

Part Number AN-686
Description APPLICATION NOTE
Manufacturers Analog Devices 
Logo Analog Devices Logo 


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AN-686
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • www.analog.com
Implementing an I2C® Reset
By Jim Greene
The I2C bus is a high integrity, robust serial bus used for
control purposes in many systems. The primary compo-
nents that make up a system are at least one master and
one slave. Under normal conditions, everything works
fine; however, it is the abnormal conditions that gener-
ate problems.Two questions present themselves when a
problem arises: Is the problem device or system related,
or some combination of both? What, if anything, can be
done about it?
Hard device failures are relatively easy to isolate. Perhaps
a function does not work, proper power cycling does not
resolve the issue, pins are stuck high or low, and so on.
System related problems sometimes disguise themselves
as device failures, or worse, are intermittent. It is the latter
area that this application note examines because it repre-
sents the majority of bus fault conditions.
Perhaps a brief description of the I2C bus is in order. The
I2C (inter integrated circuit) bus was developed and pat-
ented by Philips. It allows devices to communicate over
an open-drain (or open-collector) 2-wire serial bus. Inter-
facing is simple; serial data (SDA) and serial clock (SCL)
are the only signals that traverse the circuit board. Due to
the low speed (literally dc to 400 kB/s) problems associ-
ated with routing, transmission line effects and matching
are nonexistent. The limiting factor is bus capacitance,
which is limited to 400 pF.
The following terms are used to describe the I2C bus:
Master—the device that initiates a message, and defines
the direction of the I2C bus.The master is also responsible
for the generation of the clock (SCL). (9 clocks per byte: 8
for data and 1 for the acknowledge.)
Slave—a device with an address that is addressed by a
master.
Start—a bus condition in which the SCL line is high and
the SDA line transitions from a high to a low. It is the
first operation on the bus and is always followed by an
address. The least significant bit determines the direc-
tion of the bus. A high tells the slave that the bus will
read, while an LSB = 0 identifies a write to the specified
address.
Stop—the condition opposite Start, under which the SCL
line is high while the SDA line goes from a low to a high
REV. 0
state. It is the only method of ending a transmission after
the reception of a byte.
Byte Width—all bytes are 8 bits wide, with no exceptions.
Message Length—technically there is no maximum length
for a message; a minimum message consists of 2 bytes
(an address and a data byte).
Wait State—this condition is rarely used, but is worth
understanding. Once the SCL line is low, a device may
continue to hold it low to identify a wait state. The wait
state permits slow devices to not lose synchronization
with the transmitting device. An example is writing many
bytes to an E2PROM; another is a processor holding off
data from a slave to handle an interrupt.
Acknowledge—The “ACK” is the condition under which
the master generates a 9th clock pulse on the SCL line
(for each byte) while the receiving device pulls the SDA
line low in order to signify that the last byte was received.
A “NAK” is only generated by the master; it signals the
slave that no additional data need be sent. A NAK is used
prior to a STOP to prevent the slave from driving the bus
with additional data when the master is about to termi-
nate the communication.
Frequently the master, which is usually a microcontroller
or a gate array, will be interrupted in the middle of its
communication with an I2C slave and, upon return, find
a stuck bus. Initially this looks like a device problem, but
it is not. The slave is still waiting to send the remainder
of the data requested by the master. The problem is that
the master has forgotten where it was when it was inter-
rupted or reset. An extraneous reset on the processor will
generally create this condition, especially if the processor
cannot save its status. At this point, the slave will have
put the next bit out on the SDA line (because the SCL line
may have dropped to a low on reset) and awaits the next
clock on SCL. Of course the processor does not send it,
and as a result this slave just waits and waits. If the bit
the slave puts on the SDA line is a 0, the newly awakened
processor sees what appears to be a hung bus. The bus
is in a nonoperational mode; however, it is not due to the
slave. It is the processor’s fault for not finishing the mes-
sage it started. Generating graceful resets is not within
the scope of this application note.


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