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What is 24AA025?

This electronic component, produced by the manufacturer "Microchip Technology", performs the same function as "(24AA024 / 24AA025) 2K I2C Serial EEPROM".


24AA025 Datasheet PDF - Microchip Technology

Part Number 24AA025
Description (24AA024 / 24AA025) 2K I2C Serial EEPROM
Manufacturers Microchip Technology 
Logo Microchip Technology Logo 


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24AA024/24LC024/24AA025/24LC025
2K I2CSerial EEPROM
Device Selection Table
Part
Number
VCC Range
Max
Clock
Temp. Write
Range Protect
24AA024 1.8V - 5.5V 400 KHz(1)
24AA025 1.8V - 5.5V 400 KHz(1)
I
I
Yes
No
24LC024 2.5V - 5.5V 400 KHz I
Yes
24LC025 2.5V - 5.5V 400 KHz I
No
Note 1: 100 KHz for VCC < 2.5V
Features
• Single supply with operation from 1.8V to 5.5V
• Low-power CMOS technology
- 1 mA active current typical
- 1 µA standby current typical at 5.5V
• Organized as a single block of 256 bytes (256 x 8)
• Hardware write protection for entire array
(24XX024)
• 2-wire serial interface bus, I2C™ compatible
• 100 kHz and 400 kHz clock compatibility
• Page write buffer for up to 16 bytes
• Self-timed write cycle (including auto-erase)
• 10 ms max. write cycle time
• Address lines allow up to eight devices on bus
• 1,000,000 erase/write cycles
• ESD protection > 4,000V
• Data retention > 200 years
• 8-pin PDIP, SOIC, TSSOP and MSOP packages
• Available for extended temperature ranges
- Industrial (I): -40°C to +85°C
Pin Function Table
Name
VSS
SDA
SCL
VCC
A0, A1, A2
WP
Function
Ground
Serial Data
Serial Clock
1.8V to 5.5V Power Supply
Chip Selects
Hardware Write-Protect (24LC024)
Description
The Microchip Technology Inc. 24AA024/24LC024/
24AA025/24LC025 is a 2 Kbit Serial Electrically
Erasable PROM with a voltage range of 1.8V to 5.5V.
The device is organized as a single block of 256 x 8-bit
memory with a 2-wire serial interface. Low current
design permits operation with typical standby and
active currents of only 1 µA and 1 mA, respectively.
The device has a page write capability for up to 16
bytes of data. Functional address lines allow the
connection of up to eight 24AA024/24LC024/
24AA025/24LC025 devices on the same bus for up to
16K bits of contiguous EEPROM memory. The device
is available in the standard 8-pin PDIP, 8-pin SOIC
(150 mil), TSSOP and MSOP packages.
Package Types
PDIP/SOIC
A0 1
8 VCC
A1 2
A2 3
7 WP*
6 SCL
VSS 4
TSSOP/MSOP
A0
A1
A2
VSS
1
2
3
4
5 SDA
8 VCC
7 WP*
6 SCL
5 SDA
Block Diagram
A0 A1 A2
WP*
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
VCC
VSS
EEPROM
Array
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
Note:
*WP pin available only on 24XX024. This pin
has no internal connection on 24XX025.
2004 Microchip Technology Inc.
DS21210G-page 1

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24AA025 equivalent
24AA024/24LC024/24AA025/24LC025
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited, (though only the last sixteen will
be stored when performing a write operation). When an
overwrite does occur, it will replace data in a first-in
first-out fashion.
4.5 Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24AA024/24LC024/24AA025/
24LC025 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generating
an Acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to generate
the Stop condition (Figure 4-2).
FIGURE 4-1:
SCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(C) (D)
(C) (A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL 1 2 3 4 5 6 7 8 9 1 2 3
Stop
Condition
SDA
Data from transmitter
Transmitter must release the SDA line at this point allowing
the Receiver to pull the SDA line low to acknowledge the
previous eight bits of data.
Data from transmitter
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
2004 Microchip Technology Inc.
DS21210G-page 5


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Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 24AA025 electronic component.


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