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What is ADG1434?

This electronic component, produced by the manufacturer "Analog Devices", performs the same function as "(ADG1433 / ADG1434) Triple/Quad SPDT".


ADG1434 Datasheet PDF - Analog Devices

Part Number ADG1434
Description (ADG1433 / ADG1434) Triple/Quad SPDT
Manufacturers Analog Devices 
Logo Analog Devices Logo 


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4 Ω RON, Triple/Quad SPDT
±15 V/+12 V/±5 V iCMOS® Switches
ADG1433/ADG1434
FEATURES
4.7 Ω maximum on resistance @ 25°C
0.5 Ω on resistance flatness
33 V supply maximum ratings
Fully specified at ±15 V/+12 V/±5 V
3 V logic compatible inputs
Rail-to-rail operation
Break-before-make switching action
16-/20-lead TSSOP and 4 mm × 4 mm LFCSP_VQ packages
APPLICATIONS
Relay replacement
Audio and video routing
Automatic test equipment
Data acquisition systems
Temperature measurement systems
Avionics
Battery-powered systems
Communication systems
Medical equipment
GENERAL DESCRIPTION
The ADG1433 and ADG1434 are monolithic industrial-CMOS
(iCMOS) analog switches comprising three independently
selectable single-pole, double-throw (SPDT) switches and four
independently selectable SPDT switches, respectively.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An EN
input on the ADG1433 (LFCSP and TSSOP packages) and
ADG1434 (LFCSP package only) is used to enable or disable the
device. When disabled, all channels are switched off.
The iCMOS modular manufacturing process combines high
voltage, complementary metal-oxide semiconductor (CMOS)
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation
in a footprint that no other generation of high voltage parts has
been able to achieve. Unlike analog ICs using conventional
FUNCTIONAL BLOCK DIAGRAMS
ADG1433
S1A
D1
S1B
S3B
D3
S2B S3A
D2
S2A
LOGIC
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR
A “1” INPUT LOGIC.
Figure 1. ADG1433 TSSOP and LFCSP_VQ
ADG1434
S1A S4A
D1 D2
S1B S4B
IN1 IN4
IN2 IN3
S2B S3B
D2 D3
S2A S3A
ADG1434
S1A S4A
D1 D2
S1B S4B
S2B S3B
D2 D3
S2A S3A
LOGIC
SWITCHES SHOWN FOR
A “1” INPUT LOGIC.
Figure 2. ADG1434 TSSOP
IN1 IN2 IN3 IN4 EN
SWITCHES SHOWN FOR
A “1” INPUT LOGIC.
Figure 3. ADG1434 LFCSP_VQ
CMOS processes, iCMOS components can tolerate high supply
voltages while providing increased performance, dramatically
lower power consumption, and reduced package size.
The ultralow on resistance and on resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications, where low distortion is critical. iCMOS
construction ensures ultralow power dissipation, making the parts
ideally suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 4.7 Ω maximum on resistance.
2. 0.5 Ω on resistance flatness.
3. 3 V logic compatible digital input VIH = 2.0 V, VIL = 0.8 V.
4. 16-/20-lead TSSOP and 4 mm × 4 mm LFCSP_VQ packages.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

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ADG1434 equivalent
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ADG1433/ADG1434
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ΔRON
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (OFF)
Drain Off Leakage, ID (OFF)
Channel On Leakage, ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANS
Break-Before-Make Time Delay, tD
tON(EN)
tOFF(EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
3 dB Bandwidth
Insertion Loss
CS (OFF)
CD (OFF)
CD, CS (ON)
POWER REQUIREMENTS
IDD
IDD
VDD
−40°C to −40°C to
+25°C +85°C +125°C1
6
8 9.5
0.55
0.82 0.85
1.5
2.5 2.5
0 to VDD
11.2
1.1
2.8
±0.04
±0.3
±0.04
±0.3
±0.06
±0.4
±0.6
±0.6
±0.8
±3
±3
±8
±0.005
4
2.0
0.8
±0.1
200
255 310
80
210
270 320
70
86 95
−10
–70
–70
135
0.5
25
45
80
350
55
360
105
0.002
260
1
440
5/16.5
1 Temperature range for Y version: −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Unit Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 0 V to 10 V, IS = −10 mA, see Figure 25
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 26
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 26
VS = VD = 1 V or 10 V, see Figure 27
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
V min/max
RL = 100 Ω, CL = 35 pF
VS = 8 V, see Figure 28
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 29
RL = 100 Ω, CL = 35 pF
VS = 8 V, see Figure 30
RL = 100 Ω, CL = 35 pF
VS = 8 V, see Figure 30
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
RL = 50 Ω, CL = 5 pF, see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
VSS = 0 V, GND = 0 V
Rev. 0 | Page 5 of 20


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