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PDF MB88101A Data sheet ( Hoja de datos )
| Número de pieza | MB88101A | |
| Descripción | A/D Converter | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-13105-2E
Linear IC Converter
CMOS
A/D Converter
(With 4-channel Input at 12-bit Resolution)
MB88101A
s DESCRIPTION
The MB88101A is an analog-to-digital converter that converts its analog input to a 12-bit digital value and outputs
it as serial data.
The MB88101A employs a successive approximation method for A/D conversion.
The MB88101A has four input channels selectable for analog input under control of the dedicated external pins.
The MB88101A can be switched to a mode for continuous A/D conversion, in which it outputs serial data from the
MSB or LSB selectable depending on the mode setting.
s FEATURES
• 4-channel analog input
• One analog input channel selectable for conversion by external control
• CR-type successive approximation system with a sample-and-hole circuit
• 12-bit resolution
• Serial output of 12-bit digital data
• Capable of continuous conversion (continuous conversion mode)
• MSB or LSB selectable for serial output
• CMOS process
• Package options of 16-pin DIP, SSOP, and SOP available
s PACKAGES
16-pin Plastic DIP
16-pin Plastic SSOP
16-pin Plastic SOP
(DIP-16P-M04)
(FPT-16P-M05)
(FPT-16P-M06)
1 page  
MB88101A
s FUNCTIONAL DESCRIPTION
1. Mode 1
This mode sets the DO pin to “L” and stops conversion upon completion of conversion of 12 bits. To restart
conversion, set CS to “H” once then to “L”. In this mode, converted data is output from the MSB.
• Timing diagram
CS
MOD0, 1
C0, C1
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12
Sampling
Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Trial
Sampling
Hi-z
DO
Hi-z
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Hi-z
SAMP
Hi-z
2. Mode 2
This mode continues conversion until CS becomes “H” after it becomes “L”. Converted data is output from the
LSB, with the first piece of converted data output 20 clock cycles after CS becomes “L”. Changing the channel
select pin settings before starting sampling of one analog input allows another to be converted.
• Timing diagram
CS
MOD0, 1
C0, C1
CLK
Bit
Trial
DO
SAMP
Mode 2
AN0
AN2
AN1
16CLK
MSB (AN0) ⇒ LSB
Hi-z
Hi-z
MSB (AN2) ⇒ LSB
LSB (AN0) ⇒ MSB
MSB (AN1) ⇒ LSB
LSB (AN2) ⇒ MSB
Hi-z
Hi-z
5
5 Page 
MB88101A
s TIMING DIAGRAM
(1) Input clock timing
CLK
t CLK
t CKH
t Cf t CKL
t Cr
Evaluation levels are 80% and 20% of the VCC.
(2) A/D startup timing
CLK
CS
MOD0, 1
C0, C1
SAMP
DO
tCSS
tCSH
tMOS tMOH
tCHS
Hi-z
tSVE
Hi-z
tDVE
tSHD
tCHH
tSLD
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MB88101A.PDF ] | |
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