PDF CY7C1325 Data sheet ( Hoja de datos )

Número de pieza	CY7C1325
Descripción	256K x 18 Synchronous 3.3V Cache RAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com CY7C1325 256K x 18 Synchronous 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 256K by 18 common I/O • Fast clock-to-output times — 7.5 ns (117-MHz version) • Two-bit wrap-around counter supporting either inter- leaved or linear burst sequence • Separate processor and controller address strobes pro- vides direct interface with the processor and external cache controller • Synchronous self-timed write • Asynchronous output enable • I/Os capable of 2.5–3.3V operation • JEDEC-standard pinout • 100-pin TQFP packaging • ZZ “sleep” mode The CY7C1325 is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap- tures the first address in a burst and increments the address automatically for the rest of the burst access. The CY7C1325 allows both an interleaved or linear burst se- quences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the Cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. A synchronous self-timed write mechanism is provided to sim- plify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control. Logic Block Diagram CLK ADV ADSC ADSP A[17:0] GW BWE BW 1 18 BW 0 CE1 CE2 CE3 MODE (A0,A1) 2 BURST Q0 CE COUNTER CLR Q1 DaADtaDRSEhSSeeQt4U1.6com CE D REGISTER 16 D DQ[15:8] Q BYTEWRITE REGISTERS D DQ[7:0] Q BYTEWRITE REGISTERS D CE ENABLE REGISTER Q CLK 18 256K X 18 MEMORY ARRAY 18 18 DataShee OE ZZ SLEEP CONTROL Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Intel and Pentium are registered trademarks of Intel Corporation. DataSheet4U.com 7C1325-117 7.5 350 10.0 7C1325-100 8.0 325 10.0 7C1325-80 8.5 300 10.0 INPUT REGISTERS CLK DQ[15:0] DP[1:0] 7C1325-50 11.0 250 10.0 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 10, 2000 DataSheet4 U .com 1 page www.DataSheet4U.com CY7C1325 Burst Sequences This family of devices provide a 2-bit wrap-around burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Table 1. Counter Implementation for the Intel® Pentium®/80486 Processor’s Sequence First Address AX + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 00 11 10 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 10 01 00 Table 2. Counter Implementation for a Linear Sequence First Address AX + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 10 11 00 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ HIGH places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Ac- cesses pending when entering the “sleep” mode are not con- sidered valid nor is the completion of the operation guaran- teed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. et4U.com DataSheet4U.com DataShee DataSheet4U.com DataSheet4 U .com 5 5 Page www.DataSheet4U.com Timing Diagrams (continued) Read Cycle Timing[14, 16] CY7C1325 et4U.com CLK Single Read tCYC tCH Burst Read Unselected Pipelined Read tADS tADH tCL ADSP ignored with CE1 inactive ADSP tADS ADSC ADV tADVS tADH tAS tADVH ADD RD1 RD2 tAH GW tWS tWH WE CE1 tCES tCEH ADSC initiated read Suspend Burst RD3 DataSheet4U.com tWS tWH CE1 masks ADSP CE2 tCES CE3 tCES OE Data Out Unselected with CE2 tCEH tCEH tEOV tOEHZ tCDV 11aa tCLZ tDOH 2a 2b = DON’T CARE 2c 2c 2d = UNDEFINED 3a tCHZ DataShee Note: 16. RDx stands for Read Data from Address X. DataSheet4U.com DataSheet4 U .com 11 11 Page

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