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This electronic component, produced by the manufacturer "Xilinx", performs the same function as "(XC2Vxxx) Virtex-II Platform FPGAs: Complete Data Sheet".

XC2V6000 Datasheet PDF - Xilinx

Part Number XC2V6000
Description (XC2Vxxx) Virtex-II Platform FPGAs: Complete Data Sheet
Manufacturers Xilinx 
Logo Xilinx Logo 

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R Virtex™-II Platform FPGAs:
Complete Data Sheet
DS031 August 1, 2003
0 0 Product Specification
This document includes all four modules of the Virtex-II Platform FPGA data sheet.
Module 1:
Introduction and Overview
DS031-1 (v2.0) August 1, 2003
7 pages
• Summary of Features
• General Description
• Device/Package Combinations and Maximum I/O
• Ordering Information
Module 2:
Functional Description
DS031-2 (v3.0) August 1, 2003
40 pages
• Detailed Description
• Digitally Controlled Impedance (DCI)
• Configurable Logic Blocks (CLBs)
• Sum of Products
• 3-State Buffers
• 18-Kb Block SelectRAM™ Resources
• 18-Bit x 18-Bit Multipliers
• Global Clock Multiplexer Buffers
• Digital Clock Manager (DCM)
• Active Interconnect Technology
• Creating a Design
• Configuration
Module 3:
DC and Switching Characteristics
DS031-3 (v3.0) August 1, 2003
38 pages
• Electrical Characteristics
• Performance Characteristics
• Switching Characteristics
• Pin-to-Pin Output Parameter Guidelines
• Pin-to-Pin Input Parameter Guidelines
• DCM Timing Parameters
Module 4:
Pinout Information
DS031-4 (v2.0) August 1, 2003
225 pages
• Pin Definitions
• Pinout Tables
- CS144 Chip-Scale BGA Package
- FG256 Fine-Pitch BGA Package
- FG456 Fine-Pitch BGA Package
- FG676 Fine-Pitch BGA Package
- BG575 Standard BGA Package
- BG728 Standard BGA Package
- FF896 Flip-Chip Fine-Pitch BGA Package
- FF1152 Flip-Chip Fine-Pitch BGA Package
- FF1517 Flip-Chip Fine-Pitch BGA Package
- BF957Flip-Chip BGA Package
IMPORTANT NOTE: The Virtex-II Platform FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" pane for easy
navigation in this volume.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031 August 1, 2003
Product Specification

XC2V6000 equivalent
R Virtex™-II Platform FPGAs: Introduction and Overview
• GTL and GTLP
• HSTL (Class I, II, III, and IV)
• SSTL (3.3V and 2.5V, Class I and II)
• AGP-2X
The digitally controlled impedance (DCI) I/O feature auto-
matically provides on-chip termination for each I/O element.
The IOB elements also support the following differential sig-
naling I/O standards:
Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:
• Two function generators (F & G)
• Two storage elements
• Arithmetic logic gates
• Large multiplexers
• Wide function capability
• Fast carry look-ahead chain
• Horizontal cascade chain (OR gate)
The function generators F & G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM memory.
In addition, the two storage elements are either edge-trig-
gered D-type flip-flops or level-sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Block SelectRAM Memory
The block SelectRAM memory resources are 18 Kb of
dual-port RAM, programmable from 16K x 1 bit to 512 x 36
bits, in various depth and width configurations. Each port is
totally synchronous and independent, offering three
"read-during-write" modes. Block SelectRAM memory is
cascadable to implement large embedded storage blocks.
Supported memory configurations for dual-port and sin-
gle-port modes are shown in Table 3.
Table 3: Dual-Port And Single-Port Configurations
16K x 1 bit
2K x 9 bits
8K x 2 bits
1K x 18 bits
4K x 4 bits
512 x 36 bits
A multiplier block is associated with each SelectRAM mem-
ory block. The multiplier block is a dedicated 18 x 18-bit
multiplier and is optimized for operations based on the block
SelectRAM content on one port. The 18 x 18 multiplier can
be used independently of the block SelectRAM resource.
Read/multiply/accumulate operations and DSP filter struc-
tures are extremely efficient.
Both the SelectRAM memory and the multiplier resource
are connected to four switch matrices to access the general
routing resources.
Global Clocking
The DCM and global clock multiplexer buffers provide a
complete solution for designing high-speed clocking
Up to 12 DCM blocks are available. To generate de-skewed
internal or external clocks, each DCM can be used to elimi-
nate clock distribution delay. The DCM also provides 90-,
180-, and 270-degree phase-shifted versions of its output
clocks. Fine-grained phase shifting offers high-resolution
phase adjustments in increments of 1/256 of the clock
period. Very flexible frequency synthesis provides a clock
output frequency equal to any M/D ratio of the input clock
frequency, where M and D are two integers. For the exact
timing parameters, see Virtex-II Electrical Characteris-
Virtex-II devices have 16 global clock MUX buffers, with up
to eight clock nets per quadrant. Each global clock MUX
buffer can select one of the two clock inputs and switch
glitch-free from one clock to the other. Each DCM block is
able to drive up to four of the 16 global clock MUX buffers.
Routing Resources
The IOB, CLB, block SelectRAM, multiplier, and DCM ele-
ments all use the same interconnect scheme and the same
access to the global routing matrix. Timing models are
shared, greatly improving the predictability of the perfor-
mance of high-speed designs.
There are a total of 16 global clock lines, with eight available
per quadrant. In addition, 24 vertical and horizontal long
lines per row or column as well as massive secondary and
local routing resources provide fast interconnect. Virtex-II
buffered interconnects are relatively unaffected by net
fanout and the interconnect layout is designed to minimize
Horizontal and vertical routing resources for each row or
column include:
• 24 long lines
• 120 hex lines
• 40 double lines
• 16 direct connect lines (total in all four directions)
DS031-1 (v2.0) August 1, 2003
Product Specification
Module 1 of 4


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