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What is UPD485506?

This electronic component, produced by the manufacturer "NEC", performs the same function as "LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT".


UPD485506 Datasheet PDF - NEC

Part Number UPD485506
Description LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
Manufacturers NEC 
Logo NEC Logo 


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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD485506
LINE BUFFER
5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
Description
The µPD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either
5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power
consumption.
The µPD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and
digital copiers.
Moreover, the µPD485506 can execute read and write operations independently on an asynchronous basis. Thus
the µPD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for
the synchronization of multiple input signals.
There are four versions, E, K, P, X and L. This data sheet can be applied to the version X and L. These versions
operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping).
Features
• 5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode)
• Asynchronous read/write operations available
• Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns)
15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns)
• Power supply voltage VCC = 5.0 V ±0.5 V
• Suitable for sampling two lines of A3 size paper (16 dots/mm)
• All input/output TTL compatible
• 3-state output
• Full static operation; data hold time = infinity
Ordering Information
Part Number
µPD485506G5-25-7JF
µPD485506G5-35-7JF
R/W Cycle Time
25 ns
35 ns
Package
44-pin plastic TSOP (II) (10.16 mm (400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. M10060EJ7V0DSJ1 (7th edition)
Date Published December 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1994

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UPD485506 equivalent
µPD485506
2. Operation Mode
µPD485506 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).
For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).
2.1 Mode Set Cycle (5,048 words by 16 bits or 10,096 words by 8 bits organization)
µPD485506 has a capability of selecting from two operation modes by judging the MD level when RSTW or
RSTR is enabled in the reset cycle.
MD Level
“L”
“H”
Bit Configuration
5,048 words by 16 bits
10,096 words by 8 bits
Data Inputs/Outputs
DIN0 - DIN15
DOUT0 - DOUT15
DIN0 - DIN7
DOUT0 - DOUT7
Control Signal
WCK, WE, RSTW
RCK, RE, RSTR
WCK, WE, RSTW
RCK, RE, RSTR
Caution Don’t change the MD level during a reset cycle. (See Figure 4.6, 7, 8, 9 Mode Set Cycle Timing
Chart)
5,048 Words by 16 Bits FIFO
WCK WE RSTW
DIN0 - DIN15
5,048 Words
by
16 Bits
DOUT0 - DOUT15
10,096 Words by 8 Bits FIFO
WCK
RCK RE RSTR OE
WE
RSTW
DIN0 - DIN7
10,096 Words by 8 Bits
RCK
RE
RSTR
OE
Remark Fix DIN8 - DIN15 to “L” or “H” level in the 10,096 words by 8 bits mode.
Data Sheet M10060EJ7V0DS00
DOUT0 - DOUT7
5


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Part Details

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Featured Datasheets

Part NumberDescriptionMFRS
UPD485505The function is LINE BUFFER 5K-WORD BY 8-BIT. NECNEC
UPD485506The function is LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT. NECNEC

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