PDF CY7C1380C Data sheet ( Hoja de datos )

Número de pieza	CY7C1380C
Descripción	18-Mb (512K x 36/1M x 18) Pipelined SRAM
Fabricantes	Cypress Semiconductor
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CY7C1380C CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200,166 and 133MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.8 ns (for 225-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 166-MHz device) — 4.2 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable Enables (CE2 and CE3 [2]), Burst (CCoEn1t)r,oldienpptuht-se(xApDanSsCio, nADCShPip, a(GndWA).DAVs)y, nWchrirtoenEonuasbilnepsu(tBsWinXc,luadned BWE), and the Output Global Enable Write (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1380C/CY7C1382C operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Maximum Access Time 2.6 2.8 3.0 3.4 4.2 Maximum Operating Current 350 325 300 275 245 Maximum CMOS Standby Current 70 70 70 70 70 Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 , CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable. Unit ns mA mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05237 Rev. D Revised February 26, 2004 1 page CY7C1380C CY7C1382C Pin Configurations (continued) 123 A NC / 288M B NC A A CE1 CE2 C DQPC NC VDDQ D DQC DQC VDDQ E DQC DQC VDDQ F DQC DQC VDDQ G DQC DQC VDDQ H NC VSS NC J DQD DQD VDDQ K DQD DQD VDDQ L DQD DQD VDDQ M DQD DQD VDDQ N DQPD NC VDDQ P NC NC / 72M A R MODE NC / 36M A 123 A NC / 288M B NC A A CE1 CE2 C NC NC VDDQ D NC DQB VDDQ E NC DQB VDDQ F NC DQB VDDQ G NC DQB VDDQ H NC VSS NC J DQB NC VDDQ K DQB NC VDDQ L DQB NC VDDQ M DQB NC VDDQ N DQPB NC VDDQ P NC NC / 72M A R MODE NC / 36M A 165-ball fBGA CY7C1380C (512K x 36) 4 567 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO A TMS A0 TCK CY7C1382C (1M x 18) 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A AA 10 11 AA A NC / 144M NC DQPA NC DQA NC DQA NC DQA NC DQA NC ZZ DQA NC DQA NC DQA NC DQA NC NC NC AA AA Document #: 38-05237 Rev. D Page 5 of 36 5 Page CY7C1380C CY7C1382C CY7C1382C:Pin Definitions (continued) Name TQFP BGA fBGA I/O Description VDDQ 4,11,20,27,54, 61,70, 77 A1,A7,F1,F7, J1,J7,M1,M7, U1,U7 C3,C9,D3,D9, I/O Power Sup- Power supply for the I/O circuitry. E3,E9, ply F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9,N3, N9 MODE 31 R3 R1 Input- Selects Burst Order. When tied to GND selects Static linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. TDO - U5 P7 JTAG serial Serial data-out to the JTAG circuit. Delivers data output on the negative edge of TCK. If the JTAG feature is Synchronous not being utilized, this pin should be left uncon- nected. This pin is not available on TQFP packages. TDI - U3 P5 JTAG serial Serial data-In to the JTAG circuit. Sampled on the input rising edge of TCK. If the JTAG feature is not being Synchronous utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not avail- able on TQFP packages. TMS TCK - - U2 R5 JTAG serial Serial data-In to the JTAG circuit. Sampled on the input rising edge of TCK. If the JTAG feature is not being Synchronous utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC 1,2,3,6,7, B1,B7, A5,B1,B4, - No Connects. Not internally connected to the die. 14,16,25, C1,C7, C1,C2,C10,D1 28,29,30, D2,D4, ,D10, 38,39, D7,E1, E1,E10,F1, 51,52,53, E6,H2, F10,G1, 56,57,66, F2,G1, G10,H1,H3,H9 75,78,79, G6,H7, ,H10,J2,J11, 95,96 J3,J5,K1, K2, K6,L4,L2,L7, K11,L2,L1,M2, M6, M11, N2,L7,P1,P6, N2,N10,N5,N7 R1, N11,P1,A1, R5,R7, B11, T1,T4,U6 P2,R2 Document #: 38-05237 Rev. *D Page 11 of 36 11 Page

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