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CTS100ELT22DG PDF Datasheet Search Results

No Part number Description ( Function ) Manufacturers PDF
1 CTS100ELT22DG
Dual CMOS/TTL to Differential PECL Translator

CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 FEATURES  0.5ns Typical Propogation Delay  <100ps Typical Output to Output Skew  Flow Through Pinouts  Differential PECL Output  RoHS Compliant Pb Free Packages BLOCK DIAGRAM DESCRIPTION The CTS100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline packaging and the low skew, dual gate design of the CTS100ELT22 makes it ideal for applications that require the translation of a clock and a data signal. The CTS100ELT22 is a direct replacement for the ON Semi MC100ELT22, MC100LVELT22 and

CTS - CTS100ELT22DG pdf datasheet
CTS
CTS100ELT22DG datasheet pdf

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CTS100ELT22 Data sheets

No Description ( Function) Manufacturers PDF
CTS100ELT22   Dual CMOS/TTL to Differential PECL Translator

CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 FEATURES  0.5ns Typical Propogation Delay  <100ps Typical Output to Output Skew  Flow Through Pinouts  Differential PECL Output  RoHS Compliant Pb Free Packages BLOCK DIAGRAM DESCRIPTION The

CTS
CTS
datasheet pdf
CTS100ELT22TG   Dual CMOS/TTL to Differential PECL Translator

CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 FEATURES  0.5ns Typical Propogation Delay  <100ps Typical Output to Output Skew  Flow Through Pinouts  Differential PECL Output  RoHS Compliant Pb Free Packages BLOCK DIAGRAM DESCRIPTION The

CTS
CTS
datasheet pdf
CTS100ELT22DG   Dual CMOS/TTL to Differential PECL Translator

CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 FEATURES  0.5ns Typical Propogation Delay  <100ps Typical Output to Output Skew  Flow Through Pinouts  Differential PECL Output  RoHS Compliant Pb Free Packages BLOCK DIAGRAM DESCRIPTION The

CTS
CTS
datasheet pdf


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