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74HC138 PDF Datasheet Search Results

No Part number Description ( Function ) Manufacturers PDF
5 74HC138
3-to-8 line decoder/demultiplexer inverting

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT138 3-to-8 line decoder/demultiplexer; inverting Product specification File under Integrated Circuits, IC06 Septembe

Philips
Philips
pdf
4 74HC138
3-to-8 line decoder/demultiplexer

74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 6 — 28 December 2015 Product data sheet 1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E

NXP
NXP
pdf
3 74HC138
3 TO 8 LINE DECODER DEMULTIPLEXER

74HC138 3 TO 8 LINE DECODER DEMULTIPLEXER Description The 74HC138 is a high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaing seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state r

Diodes
Diodes
pdf
2 74HC138A
1-OF-8 DECODER / DEMULTIPLEXER

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1-of-8 Decoder/Demultiplexer High–Performance Silicon–Gate CMOS The MC54/74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC138A decodes a three–bit Address to one–of–eight active–low outputs. This devic

Motorola
Motorola
pdf
1 74HC138D
high speed CMOS 3-to-8 DECODER

CMOS Digital Integrated Circuits Silicon Monolithic 74HC138D 74HC138D 1. Functional Description • 3-to-8 Line Decoder 2. General The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary

Toshiba
Toshiba
pdf



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