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Datasheet 48LC2M32B2 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | Category |
| 1 | 48LC2M32B2 | MT48LC2M32B2 64Mb: x32 SDRAM
SYNCHRONOUS DRAM
FEATURES
• PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burs |  MICRON | data |
48L Datasheet ( Hoja de datos ) - resultados coincidentes |
| N.º | Número de pieza | Descripción | Fabricantes | Catagory |
| 1 | 48LC16M16A2 | MT48LC16M16A2 256Mb: x4, x8, x16 SDRAM Features
Synchronous DRAM
MT48LC64M4A2 – 16 Meg x 4 x 4 banks MT48LC32M8A2 – 8 Meg x 8 x 4 banks MT48LC16M16A2 – 4 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com
Features
• PC100- and PC133-compliant �  Micron Technology data | | |
| 2 | 48LC2M32B2 | MT48LC2M32B2 64Mb: x32 SDRAM
SYNCHRONOUS DRAM
FEATURES
• PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burs MICRON data | | |
| 3 | 48LC4M32B2 | MT48LC4M32B2 128Mb: x32 SDRAM Features
SDR SDRAM
MT48LC4M32B2 – 1 Meg x 32 x 4 Banks Features
• PC100-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row a  Micron data | | |
| 4 | 48LC8M16A2 | MT48LC8M16A2 128Mb: x4, x8, x16 SDRAM
SYNCHRONOUS DRAM
FEATURES
• PC100-, and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row a Micron Technology data | | |
| 5 | 48LC8M32B2 | MT48LC8M32B2 PRELIMINARY
256Mb: x32 SDRAM
SYNCHRONOUS DRAM
FEATURES
• PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row acce Micron Technology data | | |
| 6 | 48LC8M8A2 | MT48LC8M8A2
64Mb: x4, x8, x16 SDRAM
SYNCHRONOUS DRAM
FEATURES
• PC66-, PC100-, and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hidin Micron Technology data | |
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