IS42S32200E Datasheet PDF - ISSI
| Part Number | IS42S32200E | |
| Description | SYNCHRONOUS DYNAMIC RAM | |
| Manufacturers | ISSI | |
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IS42S32200E
IS45S32200E
512K Bits x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
AUGUST 2009
FEATURES
• Clock frequency: 200, 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length:
(1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 16ms (A2 grade) or
64ms (Commercia, Industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42/45S32200E is
organized as 524,288 bits x 32-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-
speed data transfer using pipeline architecture. All inputs
and outputs signals refer to the rising edge of the clock
input.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-5 -6
5 6
10 10
200 166
100 100
5 5.5
8 8
-7 -75E Unit
7 –
10 7.5
ns
ns
143 – Mhz
100 133 Mhz
5.5 –
8 5.5
ns
ns
OPTIONS
• Packages:
86-pin TSOP-II
90-ball TF-BGA
• Operating temperature range:
Commercial (0oC to + 70oC)
Industrial (-40oC to + 85oC)
Automotive Grade, A1 (-40oC to + 85oC)
Automotive Grade, A2: (-40oC to +105oC)
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
07/23/09
1
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IS42S32200E, IS45S32200E
PIN FUNCTIONS
Symbol Pin No. (TSOP)
A0-A10
25 to 27
60 to 66
24
Type
Input Pin
BA0, BA1
CAS
CKE
22,23
18
67
Input Pin
Input Pin
Input Pin
CLK 68 Input Pin
CS
20 Input Pin
DQ0 to 2, 4, 5, 7, 8, 10,11,13
DQ31 74,76,77,79,80,82,83,85
45,47,48,50,51,53,54,56
31,33,34,36,37,39,40,42
DQM0
16,28,59,71
DQM3
DQ Pin
Input Pin
RAS 19 Input Pin
WE
17 Input Pin
Vddq 3,9,35,41,49,55,75,81 Supply Pin
Vdd
1,15,29,43
Supply Pin
GNDq 6,12,32,38,46,52,78,84 Supply Pin
GND
44,58,72,86
Supply Pin
Function (In Detail)
Address Inputs: A0-A10 are sampled during the ACTIVE
command (row-address A0-A10) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the DQM0-DQM3 pins
DQMx control thel ower and upper bytes of the DQ buffers. In read mode,
the output buffers are place in a High-Z state. During a WRITE cycle the input data
is masked. When DQMx is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. DQ0 through DQ7 are
controlled by DQM0. DQ8 throughDQ15 are controlled by DQM1. DQ16 through
DQ23 are controlled by DQM2. DQ24 through DQ31 are controlled by DQM3.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
GNDq is the output buffer ground.
GND is the device internal ground.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
07/23/09
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IS42S32200E electronic component. |
| Information | Total 30 Pages | |
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| Download | [ IS42S32200E.PDF Datasheet ] | |
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