IS45S32160B Datasheet PDF - ISSI
| Part Number | IS45S32160B | |
| Description | 512Mb SYNCHRONOUS DRAM | |
| Manufacturers | ISSI | |
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IS42S32160B
IS45S32160B
16M x 32
512Mb SYNCHRONOUS DRAM
PRELIMINARY INFORMATION
JULY 2009
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single Power supply: 3.3V + 0.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8192 refresh cycles every 16ms (A2 grade) or
64 ms (Commercial, Industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
86-pin TSOP-II
90-ball W-BGA
• Operating Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade, A1 (-40oC to +85oC)
Automotive Grade, A2 (-40oC to +105oC)
• Die Revision: B
OVERVIEW
ISSI's 512Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 512Mb SDRAM is organized in 4Meg x 32 bit x 4
Banks.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-6 -7 -75E Unit
6 7 — ns
10 10 7.5 ns
166 143 — Mhz
100 100 133 Mhz
5.4 5.4 — ns
6.5 6.5 5.5 ns
ADDRESS TABLE
Parameter
Configuration
Refresh Count Com./Ind.
A1
A2
Row Addresses
Column
Addresses
Bank Address
Pins
Autoprecharge
Pins
16M x 32
4M x 32 x 4 banks
8K / 64ms
8K / 64ms
8K / 16ms
A0 – A12
A0 – A8
BA0, BA1
A10/AP
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00B
07/01/09
1
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IS42S32160B, IS45S32160B
PIN FUNCTIONS
Symbol Type
A0-A12
Input Pin
BA0, BA1
CAS
CKE
Input Pin
Input Pin
Input Pin
CLK
CS
DQM0-DQM3
Input Pin
Input Pin
Input Pin
DQ0-DQ31
RAS
WE
Vddq
Vdd
Vssq
Vss
Input/Output Pin
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
Address Inputs: A0-A12 are sampled during the ACTIVE
command (row-address A0-A12) and READ/WRITE command (column address
A0-A8), with A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read
mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buf-
fer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH imped-
ance state whenDQMn is HIGH. This function corresponds to OE in conventional
DRAMs. In write mode, DQMn control the input buffer. When DQMn is LOW, the
corresponding buffer byte is enabled, and data can be written to the device. When
DQMn is HIGH, input data is masked and cannot be written to the device.
Data on the Data Bus is latched on these pins during Write commands, and buffered after
Read commands.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
Vssq is the output buffer ground.
Vss is the device internal ground.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00B
07/01/09
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IS45S32160B electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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