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PDF COP87L88EB Data sheet ( Hoja de datos )
| Número de pieza | COP87L88EB | |
| Descripción | 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory/ CAN Interface/ 8-Bit A/D/ and USART | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1999
COP87L88EB/RB Family
8-Bit CMOS OTP Microcontrollers with 16k or 32k
Memory, CAN Interface, 8-Bit A/D, and USART
General Description
The COP87L88EB/RB Family OTP (One Time program-
mable) microcontrollers are highly integrated COP8™ Fea-
ture core devices with 16k or 32k memory and advanced
features including a CAN 2.0B (passive) interface, A/D and
USART. These multi-chip CMOS devices are suited for appli-
cations requiring a full featured controller with a CAN inter-
face, low EMI, and versatile communications interfaces, and
as pre-production devices for ROM designs. Pin and soft-
ware compatible 8k ROM versions (COP888EB) are avail-
able as well as a range of COP8 software and hardware de-
velopment tools.
Features include an 8-bit memory mapped architecture, 10
MHz CKI (-XE = crystal oscillator) with 1µs instruction cycle,
two multi-function 16-bit timer/counters, WATCHDOG and
clock monitor, idle timer, CAN 2.0B (passive) interface,
MICROWIRE/PLUS™ serial I/O, SPI master/slave interface,
fully buffered USART, 8 bit A/D with 8 channels, two power
saving HALT/IDLE modes, MIWU, software selectable I/O
options, low EMI 4.5V to 5.5V operation, program code se-
curity, and 44/68 pin packages.
Note: A companion device with CAN interface, less I/O and
memory, A/D, and PWM timer is the COP87L84BC.
Devices included in this datasheet are:
Device
COP87L88EB
COP87L89EB
COP87L88RB
COP87L89RB
Memory (bytes)
16k OTP EPROM
16k OTP EPROM
32k OTP EPROM
32k OTP EPROM
RAM (bytes)
192
192
192
192
I/O Pins
35
58
35
58
Packages
44 PLCC
68 PLCC
44 PLCC
68 PLCC
Temperature
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
Key Features
n CAN 2.0B (passive) bus interface, with Software Power
save mode
n 8-bit A/D Converter with 8 channels
n Fully buffered USART
n Multi-input wake up (MIWU) on both Port L and M
n SPI Compatible Master/Slave Interface
n 16 or 32 kbytes of on-board OTP EPROM with security
feature
Note: Mask ROMed device with equivalent on-chip features and program
memory size of 8k is available.
n 192 bytes of on-board RAM
Additional Peripheral Features
n Idle timer (programmable)
n Two 16-bit timer, with two 16-bit registers supporting
— Processor independent PWM mode
— External Event counter mode
— Input capture mode
n WATCHDOG™ and Clock Monitor
n MICROWIRE/PLUS serial I/O
I/O Features
n Software selectable I/O options (TRI-STATE® outputs,
Push pull outputs, Weak pull up input, High impedance
input)
n Schmitt trigger inputs on Port G, L and M
n Packages: 44 PLCC with 35 I/O pins;
68 PLCC with 58 I/O pins
CPU/Instruction Set Features
n 1 µs instruction cycle time
n Fourteen multi-sourced vectored interrupts servicing
— External interrupt
— Idle Timer T0
— Timers (T1 and T2) (4 Interrupts)
— MICROWIRE/PLUS and SPI
— Multi-input Wake up
— Software Trap
— CAN interface (3 interrupts)
— USART (2 Inputs)
n Versatile easy to use instruction set
n 8-bit stacker pointer (SP) (Stack in RAM)
n Two 8-bit RegisterR Indirect Memory Pointers (B, X)
Fully Static CMOS
n Two power saving modes: HALT, IDLE
n Single supply operation: 4.5V to 5.5V
n Temperature range: −40˚C to +85˚C
Development Support
n Emulation device for COP888EB
n Real time emulation and full program debug offered by
MetaLink Development System
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
COP8™, MICROWIRE/PLUS™, WATCHDOG™ and MICROWIRE™ are trademarks of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 2000 National Semiconductor Corporation DS100044
www.national.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
6V
−0.3V to VCC +0.3V
Total Current into VCC Pins (Source)
Total Current out of GND Pins (Sink)
90 mA
100 mA
Storage Temperature Range
−65˚C to +150˚C
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C
Parameter
Conditions
Operating Voltage
Power Supply Ripple (Note 2)
Peak-to-Peak
Supply Current
CKI = 10 MHz (Note 3)
VCC = 5.5V, tc = 1 µs
HALT Current (Notes 4, 5)
IDLE Current (Note 5)
CKI = 10 MHz
VCC = 5.5V, CKI = 0 MHz
VCC = 5.5V, tc = 1 µs
Input Levels (VIH, VIL)
Reset, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pull-Up Current
Port G, L and M Input Hysteresis
VCC = 5.5V
VCC = 5.5V, VIN = 0V
(Note 8)
Output Current Levels
D Outputs
Source
Sink
CAN Transmitter Outputs
VCC = 4.5V, VOH = 3.3V
VCC = 4.5V, VOL = 1.0V
Source (Tx1)
Sink (Tx0)
All Others
VCC = 4.5V, VOH = VCC −0.1V
VCC = 4.5V, VOH = VCC − 0.6V
VCC = 4.5V, VOL = 0.1V
VCC = 4.5V, VOL = 0.6V
Source (Weak Pull-Up)
Source (Push-Pull)
Sink (Push-Pull)
TRI-STATE Leakage
Allowable Sink/Source Current per Pin
VCC = 4.5V, VOH = 2.7V
VCC = 4.5V, VOH = 3.3V
VCC = 4.5V, VOL = 0.4V
VCC = 5.5V
D Outputs (sink)
Tx0 (Sink) (Note 8)
Tx1 (Source) (Note 8)
All Other
Maximum Input Current
Room Temp
without Latchup (Notes 6, 8)
RAM Retention Voltage, Vr (Note 7)
Input Capacitance
500 ns Rise and Fall Time
(Note 8)
Load Capacitance on D2
Note 2: Maxiumum rate of voltage change must be < 0.5V/ms
Min Typ Max Units
4.5 5.5 V
0.1 VCC
16
V
mA
< 1 µA
5.5 mA
0.8VCC
0.7VCC
−40
0.05VCC
0.2VCC
0.2VCC
±2
−250
V
V
V
V
µA
µA
V
−0.4 mA
10 mA
−1.5 mA
−10 +5.0 mA
1.5 mA
10 mA
−10
−110
µA
−0.4 mA
1.6 mA
±2.0
µA
15
30
30
3
±200
mA
mA
mA
mA
mA
2.0 V
7 pF
1000
pF
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5 Page 
Functional Description (Continued)
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.
The device has 192 bytes of RAM. Sixteen bytes of RAM are
mapped as “registers” at addresses 0F0 to 0FF Hex. These
registers can be loaded immediately, and also decremented
and tested with the DRSZ (decrement register and skip if
zero) instruction. The memory pointer registers X, SP, and B
are memory mapped into this space at address locations
0FC to 0FE Hex respectively, with the other registers (other
than reserved register 0FF) being available for general us-
age.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore I/O bits and register bits can be
directly and individually set, reset and tested. The accumula-
tor (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
RESET
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports L and G, are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Port D is ini-
tialized high with RESET. The PC, CNTRL, and INCTRL
control registers are cleared. The Multi-Input Wakeup regis-
ters WKEN, WKEDG, and WKPND are cleared. The Stack
Pointer, SP, is initialized to 06F Hex.
The following initializations occur with RESET:
SPI:
SPICNTRL: Cleared
SPISTAT: Cleared
STBE Bit: Set
T1CNTRL & T2CNTRL: Cleared
ITMR: Cleared and IDLE timer period is reset to 4k Instr.
CLK
ENAD: Cleared
ADDSLT: Random
SIOR: Unaffected after RESET with power already ap-
plied.
Random after RESET at power on.
Port L: TRI-STATE
Port G: TRI-STATE
Port D: HIGH
PC: CLEARED
PSW, CNTRL and ICNTRL registers: CLEARED
Accumulator and Timer 1:
RANDOM after RESET with power already applied
RANDOM after RESET at power-on
SP (Stack Pointer): Loaded with 6F Hex
B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-up
RAM:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-up
CAN: The CAN Interface comes out of external reset in the
“error-active” state and waits until the user’s software
sets either one or both of the TXEN0, TXEN1 bits to
“1”. After that, the device will not start transmission or
reception of a frame util eleven consecutive “reces-
sive” (undriven) bits have been received. This is done
to ensure that the output drivers are not enamble dur-
ing an active message on the bus.
CSCAL, CTIM, TCNTL, TEC, REC: CLEARED
RTSTAT: CLEARED with the exception of the TBE bit which
is set to 1
RID, RIDL, TID, TDLC: RANDOM
WATCHDOG:
The device comes out of reset with both the
WATCHDOG logic and the Clock Monitor
detector armed, with the WATCHDOG ser-
vice window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor
circuits are inhibited during reset. The
WATCHDOG service window bits being ini-
tialized high default to the maximum
WATCHDOG service window of 64k tc clock
cycles. The Clock Monitor bit being initial-
ized high will cause a Clock Monitor bit be-
ing initialized high will cause a Clock Moni-
tor error following reset if the clock has not
reached the minimum specified frequency
at the termination of reset. A Clock Monitor
error will cause an active low error output on
pin G1. This error output will continue until
16 tc–32 tc clock cycles following the clock
frequency reaching the minimum specified
value, at which time the G1 output will enter
the TRI-STATE mode.
The RESET signal goes directly to the
HALT latch to restart a halted chip.
When using external reset, the external RC network shown
in Figure 6 should be used to ensure that the RESET pin is
held low until the power supply to the chip stabilizes. Under
no circumstances should the RESET pin be allowed to float.
DS100044-7
RC 5 x Power Supply Rise Time
FIGURE 6. Recommended Reset Circuit
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Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet COP87L88EB.PDF ] | |
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