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PDF VND5004CSP30 Data sheet ( Hoja de datos )
| Número de pieza | VND5004CSP30 | |
| Descripción | high-side driver | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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VND5004CSP30
Double 4mΩ high-side driver with analog CurrentSense for
automotive applications
Datasheet - production data
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Features
Max transient supply voltage
VCC 41 V
Operating voltage range
VCC 4.5 to 27 V
Max On-State resistance (per ch.) RON 4 mΩ
Current limitation (typ)
Off state supply current
ILIMH
IS
100 A
2 µA(1)
1. Typical value with all loads connected
• Automotive qualified
• General
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
• Diagnostic functions
– Proportional load current sense
– Current sense disable
– Thermal shutdown indication
• Protection
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Thermal shut down
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Reverse battery protection with self switch
on of the PowerMOS
– Electrostatic discharge protection
Applications
• All types of resistive, inductive and capacitive
loads
• Suitable for power management applications
Description
The device is a double channel high-side driver
manufactured using STMicroelectronics
proprietary VIPower® M0-5 technology. It is
intended for driving resistive or inductive loads
with one side connected to ground. Active VCC
pin voltage clamp and load dump protection
circuit protect the devices against transients on
the VCC pin.
The device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open. When CS_DIS
is driven high, the CURRENT SENSE pin is high
impedance.
Output current limitation protects the devices in
overload condition. In case of long duration
overload, the device limits the dissipated power to
a safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows
the device to recover normal operation as soon as
a fault condition disappears.
November 2015
This is information on a product in full production.
DocID027938 Rev 2
1/28
www.st.com
1 page  
VND5004CSP30
Block diagram and pin configurations
1 Block diagram and pin configurations
Figure 1. Block diagram
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Table 1. Pin functions
Function
VCC
Battery connection
OUTPUT1,2
Power output
GND
Ground connection
INPUT1,2
Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state
CURRENT SENSE1,2 Analog current sense pin, delivers a current proportional to the load current
CS_DIS
Active high CMOS compatible pin, to disable the current sense pins
DocID027938 Rev 2
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5 Page 
VND5004CSP30
Electrical specifications
Symbol
Table 9. CurrentSense (8V < VCC < 16 V)
Parameter
Test conditions
Min. Typ. Max. Unit
K1
K2
ISENSE0
VSENSE
VSENSEH
IOUT/ISENSE
IOUT = 15 A; VSENSE = 4 V; VCSD = 0 V;
Tj = -40 °C
Tj = 25 °C to 150 °C
11530 16000 19340
12730 16000 19270
IOUT/ISENSE
IOUT = 30 A; VSENSE = 4 V; VCSD = 0 V;
Tj = -40 °C
Tj = 25 °C to 150 °C
13430 16150 17880
14500 16150 17880
Analog sense current
IOUT = 0 A; VSENSE = 0 V; VCSD = 5 V;
VIN = 0 V; Tj = -40 °C to 150 °C
IOUT = 0 A; VSENSE = 0 V; VCSD = 0 V;
VIN = 5 V; Tj = -40 °C to 150 °C
0
0
5
400
Max analog sense output IOUT = 45 A; VCSD = 0 V;
voltage
RSENSE = 3.9 kΩ
5
Analog sense output
voltage in overtemperature VCC = 13 V; RSENSE = 3.9 kΩ
condition
9
µA
µA
V
V
ISENSEH
Analog sense output
current in overtemperature VCC = 13 V; VSENSE = 5 V
condition
8 mA
tDSENSE1H
Delay response time from
falling edge of CS_DIS pin
VSENSE < 4 V; 5 A < IOUT < 30 A;
ISENSE = 90% of ISENSE max
(see Figure 4)
50 100 μs
tDSENSE1L
Delay response time from
rising edge of CS_DIS pin
VSENSE < 4 V; 5 A < IOUT < 30 A;
ISENSE = 10% of ISENSE max
(see Figure 4)
5 20 μs
tDSENSE2H
Delay response time from
rising edge of INPUT pin
VSENSE < 4 V; 5 A < IOUT < 30 A;
ISENSE = 90% of ISENSE max
(see Figure 4)
270 600 μs
tDSENSE2L
Delay response time from
falling edge of INPUT pin
VSENSE < 4 V; 5 A < IOUT < 30 A;
ISENSE = 10% of ISENSE max
(see Figure 4)
100 250 μs
Figure 4. Current sense delay characteristics
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DocID027938 Rev 2
11/28
27
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