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VS6663CD PDF Datasheet - 1.3 megapixel camera module - STMicroelectronics

Part Number VS6663CD
Description 1.3 megapixel camera module
Manufacturers STMicroelectronics 
Logo STMicroelectronics Logo 
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VS6663CD datasheet, circuit
VS6663CD
Features
1280 x 960 1.3 Mpixel resolution sensor
Compact size: 6.5 mm x 6.5 mm x 4.1 mm
Short focus distance: 15 cm
MIPI CSI-2(a) (D-PHY v1.0) and CCP2 Video
data interface
Ultra low power standby mode (<15uW)
Binning 2x2 mode
Defect correction
4-channel lens shading correction
1.3 megapixel camera module
Datasheet - production data
Description
The VS6663CD is a compact camera module
designed for imaging and machine vision
applications which require a short focus distance.
It is designed to be used for high quality still
camera function and also supports video modes.
The camera silicon device is capable of
generating raw Bayer 1.3 Mpixel images up to
30 fps. The VS6663CD supports the CCI control
and CCP2 and CSI-2 data interfaces.
The module design is optimized for both footprint
and height.
A separate hardware accelerator can be
incorporated in the phone system to run the
algorithms in hardware. The specification of these
devices are contained in a separate document.
Table 1. Device summary
Order code
Package
Packing
VS6663CDQ05I/1 SMIA65 Tape and reel
a. Copyright2005 MIPI Alliance, Inc. Standard for
Camera Serial Interface 2 (CSI-2) version 1.01, limited
to 1 Gbps per lane
September 2015
This is information on a product in full production.
Doc ID027033 Rev 2
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www.st.com

1 page

VS6663CD pdf, schematic
Contents
Contents
VS6663CD
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 VS6663CD use in system with hardware coprocessor . . . . . . . . . . . . . . . 8
1.2 VS6663CD use in a system with software image processing . . . . . . . . . . 9
1.3 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1 Clock input type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.2 PLL and clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 Power-down procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.3 Internal power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.4 Power-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.5 Hardware standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.6 Software standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.7 Streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.8 Dark calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 Camera control interface (CCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 Valid register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.1 General status registers [0x0000 to 0x001F] . . . . . . . . . . . . . . . . . . . . . 23
4.2.2 Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . 24
4.2.3 Analog gain description registers [0x0080 to 0x0093] . . . . . . . . . . . . . . 24
4.2.4 Data format description registers [0x00C0 to 0x00C7] . . . . . . . . . . . . . 25
4.2.5 Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.6 Integration time and gain registers [0x0200 to 0x02FF] . . . . . . . . . . . . 27
4.2.7 Video timing registers [0x0300 to 0x03FF] . . . . . . . . . . . . . . . . . . . . . . 28
4.2.8 Image compression registers [0x0500 to 0x0501] . . . . . . . . . . . . . . . . . 29
4.2.9 Test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.10 Binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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VS6663CD equivalent
VS6663CD
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
System input clock frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-up sequence timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-down sequence timing constraints for CSI2 communications . . . . . . . . . . . . . . . . . 18
POR cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Valid register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
General status registers [0x0000 to 0x001F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Analog gain description [0x0080 to 0x0093] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data format description registers [0x00C0 to 0x00C7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Integration time and gain registers [0x0200 to 0x02FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Video timing registers [0x0300 to 0x03FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Image compression registers [0x0500 to 0x0501] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Integration time and gain parameter limit registers [0x1000 to 0x10FF]. . . . . . . . . . . . . . . 31
Video timing parameter limit registers [0x1100 to 0x11FF]. . . . . . . . . . . . . . . . . . . . . . . . . 32
Binning capability registers [0x1700 to 0x1713] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Binning register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
External clock frequency examples - 1.3 Mpixel resolution Raw10 30 fps . . . . . . . . . . . . . 43
Analog gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power supplies VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
System clock - EXTCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Power down control - XSHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CCI interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CCI interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CCP2 interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CCP2 interface - timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CSI-2 interface - high speed mode - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CSI-2 interface - low power mode - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CSI-2 interface - high speed mode - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CSI-2 interface - low power mode - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Lens design characteristics for first source lens supplier . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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VS6663CD diode, scr
VS6663CD
Overview
The module's main function is to convert the viewed scene into a data stream. The
companion processor’s function is to manage the sensor included in the module in order to
produce the best possible pictures given the module's optics and the scene itself. The
companion processor processes the data stream into a form which is easily handled by up
stream mobile baseband or multimedia processor (MMP) chipsets.
The sensor supplies high-speed clock signal to the coprocessor and provides the
embedded control sequences which allow the coprocessor to synchronize with the frame
and line level timings. The coprocessor then performs the color processing on the raw
image data from the sensor before supplying the final image data to the host.
In a coprocessor architecture, a low speed clock (external clock) is sent by the host to both
the VS6663CD and the coprocessor. This is used by the sensor in all phases of operation
and by the coprocessor during the initial stages of system boot up.
During streaming phase, the VS6663CD supplies the high-speed data qualification clock for
the coprocessor. The high-speed clock is generated using the VS6663CD embedded PLL
and is provided as the continuous data qualification clock.
1.2 VS6663CD use in a system with software image processing
The VS6663CD image sensor can also be directly connected to a baseband or multimedia
processor. No dedicated coprocessor is used in this configuration. The image processing is
done in software within the baseband processor.
Figure 3. VS6663CD in a system with software image processing
4 Ch AV
Dig filters
Dark cal
Output data I/F
CCP2 / CSI-2
Mobile
baseband
processor
Video timing
Col ADC
Pixel
array
Power
VS6663CD
CCI
Test ctrl
Sys ctrl
Clk mngt
PLL
XSHUTDOWN
EXTCLK
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VS6663CD transistor, igbt
VS6663CD
Functional description
3.2.4
3.2.5
3.2.6
Note:
3.2.7
3.2.8
Power-off
The power-off state is defined as either or both of the digital and analog supplies not
present.
Hardware standby
This is the lowest power consumption mode. CCI communications are not supported in this
mode. The PLL and the video blocks are powered down. This state is entered by pulling the
control pin XSHUTDOWN down (active low). All registers are returned to their default values
Software standby
Software standby mode preserves the contents of the CCI register map. CCI
communications are supported in this mode. The software standby mode is selected using a
serial interface command. If this state is entered from hardware standby the data pads
remain high impedance. If this state is entered from streaming then the data pads go high
impedance at the end of the current frame. The internal video timing is reset to the start of a
video frame in preparation for the enabling of active video. The values of the serial interface
registers like exposure and gain are preserved. The system clock must remain active when
communicating with the sensor.
This state is entered by releasing the device from hard reset by setting XSHUTDOWN high,
writing 0x00 to the mode control register (0x0100) or commanding a soft reset by writing
0x01 to the software reset register (0x0103).
After a soft reset or the transition of XSHUTDOWN to high, all registers are returned to their
default values.
Streaming
The VS6663CD streams live video. This mode is entered by writing 0x01 to the mode
control register (0x0100).
Dark calibration algorithm
VS6663CD runs an automatic dark calibration algorithm on the raw image data to control
the video offsets caused by dark current. This ensures that a high quality image is output
over a range of operating conditions. First frame dark level is correctly calibrated, for
subsequent frames the adjustment of the dark level is damped by a leaky integrator function
to avoid possible frame to frame flicker.
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