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VS6663CC PDF Datasheet - 1.3 megapixel camera module - STMicroelectronics

Part Number VS6663CC
Description 1.3 megapixel camera module
Manufacturers STMicroelectronics 
Logo STMicroelectronics Logo 
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VS6663CC datasheet, circuit
VS6663CC
Features
1280 x 960 1.3 Mpixel resolution sensor
Compact size: 6.5 mm x 6.5 mm x 4.1 mm
Short focus distance: 5cm
MIPI CSI-2(a) (D-PHY v1.0) and CCP2 Video
data interface
Ultra low power standby mode (<15uW)
Binning 2x2 mode
Defect correction
4-channel lens shading correction
1.3 megapixel camera module
Datasheet - production data
Description
The VS6663CC is a compact camera module
designed for imaging and machine vision
applications which require a short focus distance.
It is designed to be used for high quality still
camera function and also supports video modes.
The camera silicon device is capable of
generating raw Bayer 1.3 Mpixel images up to
30 fps. The VS6663CC supports the CCI control
and CCP2 and CSI-2 data interfaces.
The module design is optimized for both footprint
and height.
A separate hardware accelerator can be
incorporated in the phone system to run the
algorithms in hardware. The specification of these
devices are contained in a separate document.
Table 1. Device summary
Order code
Package
Packing
VS6663CCQ05I/1 SMIA65 Tape and reel
a. Copyright2005 MIPI Alliance, Inc. Standard for
Camera Serial Interface 2 (CSI-2) version 1.01, limited
to 1 Gbps per lane
October 2015
This is information on a product in full production.
Doc ID028526 Rev 1
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www.st.com

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VS6663CC pdf, schematic
Contents
Contents
VS6663CC
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 VS6663CC use in system with hardware coprocessor . . . . . . . . . . . . . . . 8
1.2 VS6663CC use in a system with software image processing . . . . . . . . . . 9
1.3 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 Clock input type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.2 PLL and clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 Power-down procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.3 Internal power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.4 Power-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.5 Hardware standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.6 Software standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.7 Streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.8 Dark calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Camera control interface (CCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Valid register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.1 General status registers [0x0000 to 0x001F] . . . . . . . . . . . . . . . . . . . . . 22
4.2.2 Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . 23
4.2.3 Analog gain description registers [0x0080 to 0x0093] . . . . . . . . . . . . . . 23
4.2.4 Data format description registers [0x00C0 to 0x00C7] . . . . . . . . . . . . . 24
4.2.5 Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.6 Integration time and gain registers [0x0200 to 0x02FF] . . . . . . . . . . . . 26
4.2.7 Video timing registers [0x0300 to 0x03FF] . . . . . . . . . . . . . . . . . . . . . . 27
4.2.8 Image compression registers [0x0500 to 0x0501] . . . . . . . . . . . . . . . . . 28
4.2.9 Test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.10 Binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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VS6663CC equivalent
VS6663CC
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System input clock frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-up sequence timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-down sequence timing constraints for CSI2 communications . . . . . . . . . . . . . . . . . 17
POR cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Valid register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General status registers [0x0000 to 0x001F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Analog gain description [0x0080 to 0x0093] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data format description registers [0x00C0 to 0x00C7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Integration time and gain registers [0x0200 to 0x02FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Video timing registers [0x0300 to 0x03FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Image compression registers [0x0500 to 0x0501] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Integration time and gain parameter limit registers [0x1000 to 0x10FF]. . . . . . . . . . . . . . . 30
Video timing parameter limit registers [0x1100 to 0x11FF]. . . . . . . . . . . . . . . . . . . . . . . . . 31
Binning capability registers [0x1700 to 0x1713] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Binning register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
External clock frequency examples - 1.3 Mpixel resolution Raw10 30 fps . . . . . . . . . . . . . 42
Analog gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power supplies VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
System clock - EXTCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power down control - XSHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CCI interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CCI interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CCP2 interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CCP2 interface - timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CSI-2 interface - high speed mode - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CSI-2 interface - low power mode - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CSI-2 interface - high speed mode - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CSI-2 interface - low power mode - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Lens design characteristics for first source lens supplier . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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VS6663CC diode, scr
VS6663CC
Overview
The module's main function is to convert the viewed scene into a data stream. The
companion processor’s function is to manage the sensor included in the module in order to
produce the best possible pictures given the module's optics and the scene itself. The
companion processor processes the data stream into a form which is easily handled by up
stream mobile baseband or multimedia processor (MMP) chipsets.
The sensor supplies high-speed clock signal to the coprocessor and provides the
embedded control sequences which allow the coprocessor to synchronize with the frame
and line level timings. The coprocessor then performs the color processing on the raw
image data from the sensor before supplying the final image data to the host.
In a coprocessor architecture, a low speed clock (external clock) is sent by the host to both
the VS6663CC and the coprocessor. This is used by the sensor in all phases of operation
and by the coprocessor during the initial stages of system boot up.
During streaming phase, the VS6663CC supplies the high-speed data qualification clock for
the coprocessor. The high-speed clock is generated using the VS6663CC embedded PLL
and is provided as the continuous data qualification clock.
1.2 VS6663CC use in a system with software image processing
The VS6663CC image sensor can also be directly connected to a baseband or multimedia
processor. No dedicated coprocessor is used in this configuration. The image processing is
done in software within the baseband processor.
Figure 3. VS6663CC in a system with software image processing
4 Ch AV
Dig filters
Dark cal
Output data I/F
CCP2 / CSI-2
Mobile
baseband
processor
Video timing
Col ADC
Pixel
array
Power
VS6663CC
CCI
Test ctrl
Sys ctrl
Clk mngt
PLL
XSHUTDOWN
EXTCLK
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VS6663CC transistor, igbt
VS6663CC
4 Camera control interface (CCI)
Camera control interface (CCI)
This chapter specifies the camera control interface (CCI). The I2C-type interface uses 1.8 V
I/O with two signals: serial data line (SDA) and serial clock line (SCL). CCI is used for
control data transfer. Clock signal (SCL) generation is performed by the master device (the
camera module is a slave device). The master device initiates data transfer. The CCI bus on
the camera module has a maximum speed of 400 Kbits/s and has a software switchable
device address.
Any internal register that can be written to, can also be read from. There are also read only
registers that contain device status information, (for example, design revision details). A
read instruction from an un-used register location will return the value 0x00. A read
instruction from the manufacturers specific registers may return any value. A write
instruction to a reserved or unused register location is illegal and the effect of such a write is
undefined. It is the responsibility of the host system to only write to register locations which
have been defined.
4.1
Valid register data types
The contents of the registers can represent a number of different data types (see Table 9).
The register map uses this coding to help with the interpretation of the contents of each
register.
Table 9. Valid register data types
Data type
Name
Range
Description
8UI
8-bit unsigned integer
0 to 255
-
8SI
8-bit signed integer
-128 to 127
Two’s complement notation
16UI
16-bit unsigned integer
0 to 65535
-
16SI
16UR
16-bit signed integer
16-bit unsigned iReal
-32768 to 32767
0 to 255.99609375
Two’s complement notation
08.08 fixed point number. 8
integer bits (MS Byte), 8
fractional bits (LS Byte)
16SR
16-bit signed iReal
-128 to 127.9960375
Two’s complement
notation, 8 fractional bits
32SF
32-bit IEEE floating-point
number
As per IEEE 754
As per IEEE 754. 1 sign bit,
8 exponent bits, 23
fractional bits
8C or 16C 8-bit or 16-bit Coded
-
This indicates that the
value is decoded to select
one of several functions or
modes.
8B or 16B 8 or 16 Bits
-
Each bit represents a
specific function or mode.
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