|
|
PDF IS61VPS25636A Data sheet ( Hoja de datos )
| Número de pieza | IS61VPS25636A | |
| Descripción | Single CYCLE DESELECT STATIC RAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IS61VPS25636A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
256K x 36, 256K x 32, 512K x 18
9 Mb SYNCHRONOUS PIPELINED,
Single CYCLE DESELECT STATIC RAM
JANUARY 2014
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex-
pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for BGA package
• Power Supply
LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%
VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5%
• JEDEC 100-Pin QFP, 119-ball BGA, and 165-
ball BGA packages
• Lead-free available
FAST ACCESS TIME
Symbol Parameter
tkq
Clock Access Time
tkc
Cycle Time
Frequency
DESCRIPTION
The ISSI IS61LPS/VPS25636A, IS61LPS25632A,
IS64LPS25636A and IS61LPS/VPS51218A are high-
speed, low-power synchronous static RAMs designed
to provide burstable, high-performance memory for com-
munication and networking applications. The IS61LPS/
VPS25636A and IS64LPS25636A are organized as
262,144 words by 36 bits. The IS61LPS25632A is
organized as 262,144 words by 32 bits. The IS61LPS/
VPS51218A is organized as 524,288 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology,
the device integrates a 2-bit burst counter, high-speed
SRAM core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence or-
der, Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH
or left floating.
250 200 166
2.6 3.1 3.5
4 5 6
250 200 166
Units
ns
ns
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. 1
Rev. M
01/14/14
1 page  
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
119 BGA PACKAGE PIN CONFIGURATION
512Kx18 (TOP VIEW)
12 3 4
A VDDQ
A
A ADSP
B NC CE2
A ADSC
C NC
A
A VDD
D DQb NC Vss NC
E NC DQb Vss CE
F VDDQ NC Vss OE
G NC DQb BWb ADV
H DQb NC Vss GW
J
VDDQ
VDD
NC
VDD
K NC DQb Vss CLK
L DQb NC Vss NC
M
VDDQ
DQb
Vss
BWE
N DQb NC Vss A1*
P NC DQPb Vss A0*
R NC
A
MODE
VDD
T NC
A
A NC
U
VDDQ
TMS
TDI
TCK
5
A
A
A
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
6
A
A
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address
Advance
ADSP
Address Status Processor
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE, CE2 Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write Controls
BWE
Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQb
DQPa-Pb
Vdd
Vddq
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
Integrated Silicon Solution, Inc.
Rev. M
01/14/14
5
5 Page 
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TRUTH TABLE(1-8)
OPERATION ADDRESS CE CE2 CE2 ZZ ADSP
Deselect Cycle, Power-Down None H X X L X
Deselect Cycle, Power-Down None L X L L L
Deselect Cycle, Power-Down None L H X L L
Deselect Cycle, Power-Down None L X L L H
Deselect Cycle, Power-Down None L H X L H
Snooze Mode, Power-Down
None X X X H X
Read Cycle, Begin Burst
External L L H L L
Read Cycle, Begin Burst
External L L H L L
Write Cycle, Begin Burst
External L L H L H
Read Cycle, Begin Burst
External L L H L H
Read Cycle, Begin Burst
External L L H L H
Read Cycle, Continue Burst
Next X X X L H
Read Cycle, Continue Burst
Next X X X L H
Read Cycle, Continue Burst
Next H X X L X
Read Cycle, Continue Burst
Next H X X L X
Write Cycle, Continue Burst
Next X X X L H
Write Cycle, Continue Burst
Next H X X L X
Read Cycle, Suspend Burst Current X X X L H
Read Cycle, Suspend Burst Current X X X L H
Read Cycle, Suspend Burst Current H X X L X
Read Cycle, Suspend Burst Current H X X L X
Write Cycle, Suspend Burst Current X X X L H
Write Cycle, Suspend Burst Current H X X L X
ADSC ADV
L X
X X
X X
L X
L X
X X
X X
X X
L X
L X
L X
H L
H L
H L
H L
H L
H L
H H
H H
H H
H H
H H
H H
WRITE OE CLK DQ
X X L-H High-Z
X X L-H High-Z
X X L-H High-Z
X X L-H High-Z
X X L-H High-Z
X X X High-Z
X L L-H Q
X H L-H High-Z
L X L-H D
H L L-H Q
H H L-H High-Z
H L L-H Q
H H L-H High-Z
H L L-H Q
H H L-H High-Z
L X L-H D
L X L-H D
H L L-H Q
H H L-H High-Z
H L L-H Q
H H L-H High-Z
L X L-H D
L X L-H D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are avail-
able on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
GW BWE BWa BWb BWc BWd
Read
H H X X X X
Read
H L H H H H
Write Byte 1
H L L H H H
Write All Bytes
H L L L L L
Write All Bytes
L X X X X X
Integrated Silicon Solution, Inc. 11
Rev. M
01/14/14
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS61VPS25636A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IS61VPS25636A | Single CYCLE DESELECT STATIC RAM | ISSI |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |