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VNQ7050AJ PDF Datasheet - Quad channel high-side driver - STMicroelectronics

Part Number VNQ7050AJ
Description Quad channel high-side driver
Manufacturers STMicroelectronics 
Logo STMicroelectronics Logo 
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VNQ7050AJ datasheet, circuit
VNQ7050AJ
Quad channel high-side driver with CurrentSense analog
feedback for automotive applications
Datasheet - production data
Features
Max transient supply voltage
Operating voltage range
Typ. on-state resistance (per Ch)
Current limitation (typ)
Stand-by current (max)
VCC 40 V
VCC 4 to 28 V
RON 50
ILIMH 27 A
ISTBY 0.5 µA
Automotive qualified
General
Quad channel smart high-side driver
with CS analog feedback
Very low standby current
Compatible with 3 V and 5 V CMOS
outputs
CurrentSense diagnostic functions
Analog feedback of load current with
high precision proportional current
mirror
Overload and short to ground (power
limitation) indication
Thermal shutdown indication
OFF-state open-load detection
Output short to VCC detection
Sense enable/disable
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Configurable latch-off on
overtemperature or power limitation
with dedicated fault reset pin
Loss of ground and loss of VCC
Reverse battery with external
components
Electrostatic discharge protection
Applications
All types of Automotive resistive, inductive
and capacitive loads
Specially intended for Automotive Signal
Lamps (up to P27W or SAE1156 or LED
Rear Combinations)
Description
The device is a quad channel high-side driver
manufactured using ST proprietary VIPower®
M0-7 technology and housed in PowerSSO-16
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and 5
V CMOS-compatible interface, providing
protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
June 2015
DocID027405 Rev 1
This is information on a product in full production.
1/42
www.st.com

1 page

VNQ7050AJ pdf, schematic
Contents
Contents
VNQ7050AJ
1 Block diagram and pin description ................................................ 5
2 Electrical specification.................................................................... 7
2.1 Absolute maximum ratings ................................................................ 7
2.2 Thermal data ..................................................................................... 8
2.3 Main electrical characteristics ........................................................... 8
2.4 Waveforms...................................................................................... 16
2.5 Electrical characteristics curves ...................................................... 19
3 Protections..................................................................................... 23
3.1 Power limitation............................................................................... 23
3.2 Thermal shutdown........................................................................... 23
3.3 Current limitation ............................................................................. 23
3.4 Negative voltage clamp................................................................... 23
4 Application information ................................................................ 24
4.1 GND protection network against reverse battery............................. 24
4.1.1 Diode (DGND) in the ground line ..................................................... 25
4.2 Immunity against transient electrical disturbances .......................... 25
4.3 MCU I/Os protection........................................................................ 25
4.4 CS - analog current sense .............................................................. 26
4.4.1 Principle of CurrentSense signal generation .................................... 27
4.4.2 Short to VCC and OFF-state open-load detection ........................... 29
5 Maximum demagnetization energy (VCC = 16 V) ........................ 31
6 Package and PCB thermal data .................................................... 32
6.1 PowerSSO-16 thermal data ............................................................ 32
7 Package information ..................................................................... 35
7.1 PowerSSO-16 package information ................................................ 35
7.2 PowerSSO-16 packing information ................................................. 37
7.3 PowerSSO-16 marking information................................................. 39
8 Order codes ................................................................................... 40
9 Revision history ............................................................................ 41
2/42 DocID027405 Rev 1

2 Page

VNQ7050AJ equivalent
VNQ7050AJ
Block diagram and pin description
1 Block diagram and pin description
Figure 1: Block diagram
VCC
FaultRST
INPUT3
INPUT2
INPUT1
INPUT0
SEL1
SEL0
SEn
CS
GND
VCC – GND
Clamp
Internal supply
Undervoltage
shut-down
Channel 3
Channel 2
Channel 1
Control & Diagnostic
Channel 0
0
Fault
VSENSEH
VCC – OUT
Clamp
Gate Driver
Current
Limitation
VON
Limitation
Power Limitation
Overtemperature
Short to VCC
Open-Load in OFF
Current
Sense
CH 1
CH 3
CH 2
CH 0 OUTPUT3
OUTPUT2
T OUTPUT1
OUTPUT0
GAPGCFT00605
Name
Table 1: Pin functions
Function
VCC Battery connection.
OUTPUT0,1,2,3 Power output.
GND
Ground connection. Must be reverse battery protected by an external diode / resistor
network.
INPUT0,1,2,3
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS
outputs. They control output switch state.
CS Analog current sense output pin delivers a current proportional to the load current.
SEn
Active high, compatible with 3 V and 5 V CMOS outputs input pin; it enables the CS
diagnostic pin.
SEL0,1
Active high, compatible with 3 V and 5 V CMOS outputs input pin; They address the
CS multiplexer.
FaultRST
Active low, compatible with 3 V and 5 V CMOS outputs input pin; it unlatches the
output in case of fault; If kept low, sets the outputs in auto-restart mode.
DocID027405 Rev 1
5/42

5 Page

VNQ7050AJ diode, scr
VNQ7050AJ
Electrical specification
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Vclamp Clamp voltage
IS = 20 mA; Tj = -40°C
IS = 20 mA; 25°C < Tj < 150°C
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 25°C
ISTBY
Supply current in Standby
at VCC = 13 V (2)
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 85°C (3)
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 125°C
tD_STBY
Standby mode blanking
time
VCC = 13 V
VIN = VOUT = VFR = VSEL0,1 = 0 V;
VSEn = 5 V to 0 V
IS(ON) Supply current
VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V;
VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 0 A
Control stage current
VCC = 13 V; VSEn = 5 V;
IGND(ON) consumption in ON state. VFR = VSEL0,1 = 0 V; VIN0,1,2,3 = 5 V;
All channels active.
IOUT0,1,2,3 = 1 A
IL(off)
Off-state output current at VIN = VOUT = 0 V; VCC = 13 V; Tj = 25°C
VCC = 13 V(1)
VIN = VOUT = 0 V; VCC = 13 V; Tj = 125°C
VF
Output - VCC diode
voltage(1)
IOUT = -2 A; Tj = 150°C
38
V
41 46 52
0.5 µA
0.5 µA
3 µA
60 300 550 µs
10 16 mA
20 mA
0 0.01 0.5
µA
03
0.7 V
Notes:
(1)For each channel.
(2)PowerMOS leakage included.
(3)Parameter specified by design; not subject to production test.
Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified)
Symbol
Parameter
Test conditions Min. Typ. Max. Unit
td(on)(1)
Turn-on delay time at Tj = 25°C
td(off)(1)
Turn-off delay time at Tj = 25°C
(dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25°C
(dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25°C
WON
Switching energy losses at turn-on (twon)
WOFF
Switching energy losses at turn-off (twoff)
RL = 6.5 Ω
RL = 6.5 Ω
RL = 6.5 Ω
RL = 6.5 Ω
10 35 120
µs
10 45 100
0.1 0.28 0.7
V/µs
0.1 0.31 0.7
— 0.26 0.35 (2) mJ
— 0.23 0.31(2) mJ
tSKEW(1)
Differential Pulse skew
(tPHL - tPLH)
RL = 6.5 Ω
-40 10 60 µs
Notes:
(1)See Figure 4: "Switching times and Pulse skew".
(2)Parameter guaranteed by design and characterization, not subject to production test
DocID027405 Rev 1
9/42

9 Page

VNQ7050AJ transistor, igbt
VNQ7050AJ
Figure 24: Turn-on voltage slope
Electrical specification
Figure 25: Turn-off voltage slope
Figure 26: Won vs Tcase
Figure 27: Woff vs Tcase
Figure 28: ILIMH vs. Tcase
Figure 29: OFF-state open-load voltage
detection threshold
DocID027405 Rev 1
21/42

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