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VNI8200XP-32 PDF Datasheet - Octal high-side smart power solid-state relay - STMicroelectronics

Part Number VNI8200XP-32
Description Octal high-side smart power solid-state relay
Manufacturers STMicroelectronics 
Logo STMicroelectronics Logo 
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VNI8200XP-32 datasheet, circuit
VNI8200XP-32
Octal high-side smart power solid-state relay with serial/parallel
selectable interface on-chip
Datasheet - production data
PowerSSO-36 package
with exposed pad down (EPD)
Features
Type
VNI8200XP-32
Vdemag(1)
VCC-45 V
RDS(on)(1)
0.11 Ω
IOUT(1)
1A
VCC
45 V
Notes:
(1)Per channel
Output current: 1 A per channel
Serial/parallel selectable interface
Short-circuit protection
8-bit and 16-bit SPI interface for IC
command and control diagnostic
Channel overtemperature detection and
protection
Thermal independence of separate channels
All type of loads (resistive, capacitive,
inductive load) are driven
Loss of GND protection
Power Good diagnostic
Undervoltage shutdown with hysteresis
Overvoltage protection (VCC clamping)
Very low supply current
Common fault open drain output
IC warning temperature detection
Channel output enable
100 mA high efficiency step-down switching
regulator with integrated boot diode
Adjustable regulator output
Switching regulator disable
5 V and 3.3 V compatible I/Os
Channel output status LED driving 4x2
multiplexed array
Fast demagnetization of inductive loads
ESD protection
Designed to meet IEC61131-2,
IEC61000-4-4 and IEC61000-4-5
Applications
Programmable logic control
Industrial PC peripheral input/output
Numerical control machines
Table 1: Device summary
Order code
Package
Packing
VNI8200XP-32
PowerSSO-36
VNI8200XPTR-32
Tube
Tape and
reel
August 2015
DocID027849 Rev 3
This is information on a product in full production.
1/43
www.st.com

1 page

VNI8200XP-32 pdf, schematic
Contents
Contents
VNI8200XP-32
1 Description....................................................................................... 6
2 Block diagram.................................................................................. 7
3 Pin connection................................................................................. 8
4 Maximum ratings ........................................................................... 10
5 Electrical characteristics .............................................................. 12
5.1 Power section.................................................................................. 12
5.2 SPI characteristics .......................................................................... 13
5.3 Switching......................................................................................... 13
5.4 Logic inputs ..................................................................................... 14
5.5 Protection and diagnostic ................................................................ 14
5.6 Step-down switching regulator ........................................................ 16
5.7 LED driving array ............................................................................ 16
6 Reverse polarity protection .......................................................... 17
7 Demagnetization energy ............................................................... 18
8 Truth table...................................................................................... 19
9 Pin function description................................................................ 20
9.1 SPI/parallel selection mode (SEL2)................................................. 20
9.2 Serial data in (SDI).......................................................................... 20
9.3 Serial data out (SDO)...................................................................... 20
9.4 Serial data clock (CLK) ................................................................... 20
9.5 Slave select..................................................................................... 21
9.6 8/16-bit selection (SEL1) ................................................................. 21
9.7 Output enable (OUT_EN)................................................................ 21
9.8 IC warning case temperature detection........................................... 22
9.9 Fault indication ................................................................................ 22
9.10 Power Good ( PG ) ........................................................................ 23
9.11 Programmable watchdog counter reset (WD) ................................. 23
10 SPI operation (SEL2 = H) .............................................................. 25
10.1 8-bit SPI mode (SEL1 = L) .............................................................. 25
10.2 16-bit SPI mode (SEL1 = H)............................................................ 25
11 LED driving array .......................................................................... 27
2/43 DocID027849 Rev 3

2 Page

VNI8200XP-32 equivalent
VNI8200XP-32
List of figures
List of figures
Figure 1: Block diagram ..............................................................................................................................7
Figure 2: Pin connection (top view) ............................................................................................................8
Figure 3: Reverse polarity protection........................................................................................................17
Figure 4: Maximum demagnetization energy vs. load current, typical values ..........................................18
Figure 5: SPI mode diagram .....................................................................................................................21
Figure 6: Output channel enable/disable behavior ...................................................................................22
Figure 7: Power Good diagnostic .............................................................................................................23
Figure 8: Watchdog reset .........................................................................................................................24
Figure 9: LED driving array .......................................................................................................................27
Figure 10: Typical circuit for switching regulation VDC-out = 3.3 V .............................................................29
Figure 11: Typical circuit for switching regulation VDC-out = 5 V ................................................................30
Figure 12: SPI directional logic convention...............................................................................................31
Figure 13: PowerSSO-36 thermal impedance vs. time ............................................................................32
Figure 14: Thermal behavior.....................................................................................................................33
Figure 15: Serial timing .............................................................................................................................34
Figure 16: dV/dt(ON) and dV/dt(OFF) time diagram test conditions ........................................................35
Figure 17: td(ON) and td(OFF) time diagram test conditions...........................................................................35
Figure 18: PowerSSO-36 package outline ...............................................................................................36
Figure 19: PowerSSO-36 package outline details ....................................................................................37
Figure 20: PowerSSO-36 package outline details (section B-B) ..............................................................37
Figure 21: PowerSSO-36 tube shipment outline ......................................................................................39
Figure 22: PowerSSO-36 tape dimension outline ....................................................................................40
Figure 23: PowerSSO-36 reel shipment outline .......................................................................................41
DocID027849 Rev 3
5/43

5 Page

VNI8200XP-32 diode, scr
VNI8200XP-32
Pin
14
15
16
17
18
19
20
21
Name
VREF
ROW0
ROW1
ROW2
ROW3
PG
FAULT
TWARN
22 FB
23 GND
24 PHASE
25 BOOT
26 NC
27 OUT8
28 OUT7
29 OUT6
30 OUT5
31 OUT4
32 OUT3
33 OUT2
34 OUT1
35 NC
36 NC
TAB TAB
Type
Analog output
Open drain
output
Open drain
output
Open drain
output
Open drain
output
Open drain
output
Open drain
output
Open drain
output
Analog input
Power output
Power output
Power output
Power output
Power output
Power output
Power output
Power output
Power output
Power output
Power supply
Pin connection
Description
Internally generated DC-DC voltage reference (to be
connected to external 10 nF capacitor)
Status channel 1-2
Status channel 3-4
Status channel 5-6
Status channel 7-8
Power Good diagnostic, active low
Fault indication, active low
IC case warning temperature detection, active low
Step-down feedback input. The output voltage,
directly connected to this pin, results in an output
voltage of 3.3 V. An external resistor divider is
required for higher output voltages
Ground
Step-down output
Step-down bootstrap voltage. Used to provide a
drive voltage, higher than the supply voltage, to
power the switch of the step-down regulator
Not connected
Channel 8 power output
Channel 7 power output
Channel 6 power output
Channel 5 power output
Channel 4 power output
Channel 3 power output
Channel 2 power output
Channel 1 power output
Not connected
Not connected
Exposed tab internally connected to VCC
DocID027849 Rev 3
9/43

9 Page

VNI8200XP-32 transistor, igbt
VNI8200XP-32
Pin function description
signal is high, slave not selected, the microcontroller should drive the CLK low (the settings
for the MCU SPI port are CPHA = 0 and CPOL = 0).
9.5 Slave select
If SEL2 = H, the slave select ( SS ) signal is used to enable the VNI8200XP-32 serial
communication shift register; data is flushed-in through the SDI pin and flushed-out from
the SDO pin only when the SS pin is low. On the SS pin falling edge the shift register
(containing the fault conditions) is frozen, so any change on the power switches status is
latched until the next SS falling edge event and the SDO output is enabled. On the SS
pin rising edge event the 8/16 bits present on the SPI shift register are evaluated and the
outputs are driven according to this frame. If more than 8/16 bits (depending on the SPI
settings) are flushed inside only the last 8/16 are evaluated; the others are flushed out from
the SDO pin after fault condition bits; in this way a proper communication is possible also in
a daisy chain configuration.
Figure 5: SPI mode diagram
9.6 8/16-bit selection (SEL1)
If SEL2 = H, SEL1 is used to select between two possible SPI configurations: the 8-bit SPI
mode (SEL1 = L) and the 16-bit SPI mode (SEL1 = H). 8/16-bit SPI operation is described
below.
9.7 Output enable (OUT_EN)
If SEL2 = H, the OUT_EN pin provides a fast way to disable all the outputs simultaneously.
When the OUT_EN pin is driven low for at least TRES, the outputs are disabled while fault
conditions in the SPI register are latched. To enable the outputs, the OUT_EN pin should
be raised and the IC should be re-programmed through the SPI interface. As fault
conditions are latched inside the IC and SPI interface also works while the OUT_EN pin is
driven low, the SPI can be used to detect if a fault condition occurred before than the reset
event.
DocID027849 Rev 3
21/43

21 Page





Information Total 30 Pages
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