PDF ST2100 Data sheet ( Hoja de datos )

Número de pieza	ST2100
Descripción	Broadband powerline communication SoC optimized
Fabricantes	STMicroelectronics
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No Preview Available ! ST2100 Broadband powerline communication SoC optimized for audio/video streaming and consumer applications Datasheet - production data  JPEG codec accelerator  Cryptographic coprocessor  Up to 40 GPIOs  Enhanced I2S (digital audio interface)  I2C master/slave mode  Master/slave SSI  Two independent UARTs  Fast IrDA®  Real-time clock TFBGA 12 x 12 x 1.2 mm  Configurable serial port (SPORT) interface for external DSP and audio codec (ADC and DAC) in I2S mode Features  Configurable HW engine for multiple HomePlug® PHY and real-time MAC layers processing supporting:  Transport stream interface (video TS)  Vectored interrupt controller (VIC)  JTAG (IEEE1149.1) interface  Three CPU instruction sets – HomePlug AV and 1.0 standards – HomePlug Green PHY™ standard Applications  Integrated analog front-end  ARM926EJ-S™ 32-bit RISC CPU up to 333 MHz The STreamPlug ST2100 is configurable for a wide range of powerline applications such as:  Smart gateway  8/16 bit DDR mobile at 166 MHz and DDR2 at 333 MHz memory controller  Powerline communication bridging, including wireless  Serial memory interface  Smart grid  8/16-bits NOR Flash/NAND Flash and SRAM  Electromobility memories controllers  In house audio/video distribution  Multichannel DMA controller  Video surveillance  Ethernet 10/100 MAC with MII interface  Home automation  USB 2.0  “Network Area Storage” (NAS)  PCI Express and S-ATA  Display panels control  Color LCD (CLCD) controller Table 1. Device summary Order code Operating temp. range Package Packing ST2100 -40 to +85 °C TFBGA 12 x 12 x 1.2 mm, pitch 0.5 mm Tray, tape and reel May 2014 This is information on a product in full production. DocID025777 Rev 1 1/39 www.st.com 1 page ST2100 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. STreamPlug ST2100 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MIFO 0-87 muxing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MFIO 88-103 muxing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MCLK crystal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 RTC crystal connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power-up and reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package outline for TFBGA 12 x 12 x 1.2 mm, 324 + 49 balls, 4R23 x 23, pitch 0.5 mm, ball 0.3 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DocID025777 Rev 1 5/39 39 5 Page ST2100 Architecture description 3.3 Memory subsystem The multiport memory controller within the memory subsystem manages DDR mobile up to 166 MHz and DDR2 up to 333 MHz external memory. Internally, it handles 5 ports supporting all the chip master ports. The multiport memory controller block has a programmable arbitration scheme and the transactions happen on a different layer from the main bus. It also offers a local FIFO to increase the throughput and reduce the latency. 3.4 Expi subsystem  PCI Express Gen1 (PCI Express standard version 1.1) single lane X1 dual mode – Root Complex mode is supported. – Endpoint mode is supported.  Serial ATA compliant with SATA/150 specifications  PHY is standard 8-bit/16-bit PIPE PHY interface 3.5 Basic subsystem  8 FIFOs and 16 high performance DMA channels with two AHB interfaces to parallelize the activity when two channels are working at the same time.  48 Kbytes of ROM (for boot procedure)  “Serial Memory Interface” (SMI) supporting external serial Flash.  Color LCD controller (CLCD) up to 1024 x 768 resolution at 24 bpp (true color) supporting STN/TFT display panels  Three pair of 16 bit general purpose timers with programmable prescaler  Watchdog timer  RTC with separate power supply allowing battery connection  Up to 104 “Multi-Function” I/Os (MFIOs) multiplexed with peripheral I/Os: – Allows a large number of possible application scenarios – Up to 40 GPIOs with interrupt capability  System controller, reset and clock generation, and miscellaneous registers array allowing a full configurability of the system. DocID025777 Rev 1 11/39 39 11 Page

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