SST25VF032B Datasheet PDF - Microchip
Part Number | SST25VF032B | |
Description | 32 Mbit SPI Serial Flash | |
Manufacturers | Microchip | |
Logo | ||
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32 Mbit SPI Serial Flash
SST25VF032B
EOL Data Sheet
SST 25 series Serial Flash family features a four-wire, SPI-compatible interface
that allows for a low pin-count package which occupies less board space and
ultimately lowers total system costs. The SST25VF032B devices are enhanced
with improved operating frequency which lowers power consumption.
SST25VF032B SPI serial flash memories are manufactured with SST's propri-
etary, high-performance CMOS SuperFlash technology. The split-gate cell
design and thick-oxide tunneling injector attain better reliability and manufactur-
ability compared with alternate approaches.
Features
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– Up to 80 MHz
• Superior Reliability
– Endurance: 100,000 Cycles
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Word Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (200 mils)
– 8-contact WSON (5 X 6 mm)
• All devices are RoHS compliant
© 2015
www.microchip.com
DS20005071B
04/15
|
|
32 Mbit SPI Serial Flash
SST25VF032B
Memory Organization
EOL Data Sheet
The SST25VF032B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable blocks.
Device Operation
The SST25VF032B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF032B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
SCK MODE 0
MODE 3
MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON'T CARE
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1327 F04.0
Figure 3: SPI Protocol
© 2015
DS20005071B
04/15
5
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Information | Total 30 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ SST25VF032B.PDF Datasheet ] |
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