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PDF M24C32S-FCU Data sheet ( Hoja de datos )
| Número de pieza | M24C32S-FCU | |
| Descripción | 32-Kbit serial I2C bus EEPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M24C32S-FCU
32-Kbit serial I²C bus EEPROM 4 balls CSP
WLCSP (CU)
Datasheet - production data
Features
• Compatible with the 400 kHz I²C protocol
• High speed 1MHz transfer rate
• Memory array:
– 32 Kbit (4 Kbyte) of EEPROM
– Page size: 32 byte
• Supply voltage range:
– 1.7 V to 5.5 V
• Operating temperature range
– -40°C / +85°C
• Write
– Byte Write within 5 ms
– Page Write within 5 ms
• Random and sequential Read modes
• Software Write protect
– Upper quarter memory array
– Upper half memory array
– Upper 3/4 memory array
– Whole memory array
• ESD protection
– Human Body Model: 4 kV
• More than 4 million Write cycles
• More than 200-years data retention
• Package
– WLCSP, RoHS and Halogen free compliant
(ECOPACK2®)
October 2015
This is information on a product in full production.
DocID026427 Rev 5
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1 page  
M24C32S-FCU
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4-bump WLCSP connections
(top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode sequence (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequence (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
aMnaxI2imC ubmusRabtums vaaxliumeuvmerfsreuqsubeunscypafCra=si4tic00cakpHazci.ta.n.c.e.
(Cbus) for
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Maximum
for an I2C
Rbus value versus bus parasitic
bus at high clock frequency . . .
capacitance
..........
(Cbus)
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AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline with BSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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M24C32S-FCU
Device operation
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
DocID026427 Rev 5
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M24C32S-FCU.PDF ] | |
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