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PDF STCOM Data sheet ( Hoja de datos )
| Número de pieza | STCOM | |
| Descripción | Powerline communication and application system-on-chip | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STCOM
Powerline communication and application system-on-chip
TQFP176 (20 x 20 x 1 mm)
Features
Integrated differential PLC analog front-end
– PGA with automatic gain control and ADC
– Current DAC with transmission predriver
– Digital transmission level control
– Zero crossing comparator
– Up to 500 kHz PLC signal bandwidth
Integrated dual line driver
– 14 V p-p single ended, 28 V p-p differential
output range
– Very high linearity for EMC compliance
– Externally configurable amplifier topology
– 1 A rms max. current
– Embedded overtemperature protection
– Suitable for all PLC signals up to 500 kHz
Fully reprogrammable real-time engine (RTE)
modem for PLC standards up to 500 kHz
Integrated application core: ARM® 32-bit
Cortex™-M4F CPU
– 96 MHz maximum frequency
– 8-channel direct memory access controller
– 8-region memory protection unit
– Serial wire and JTAG interfaces
– Cortex-M4 Embedded Trace Macrocell™
– Up to 86 multiplexed GPIOs
– 11 timers
– 1 flexible CRC calculation unit
Datasheet - production data
– 5 USARTs (ISO 7816 compliant), 5 SPI,
3 I2C
– 12-bit general purpose ADC with
6 channels
Cryptographic engine
– AES 128/192/256 engine
– True random number generator
Memories
– 640 kB or 1 MB of embedded Flash
– 128 kB of embedded SRAM
– 8 kB of embedded shared RAM
– Flexible static memory controller
Clock management
– 24 MHz external crystal for system clock
with internal QFS synthesizer
– 32.768 kHz external crystal for RTC
Power management
– 3.3 V and 8 - 18 V external supply voltages
– 1.2 V and 5 V integrated linear regulators
– Normal and low power modes
Real-time clock (RTC)
– VBAT supply with battery health monitoring
for RTC and backup registers
-40 °C to +85 °C operating temperature range
Applications
Smart metering, smart grid and “Internet of
Things” applications
Compliant with CENELEC, FCC, ARIB
regulations
October 2015
This is information on a product in full production.
DocID028515 Rev 1
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1 page  
STCOM
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
STCOM basic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STCOM detailed architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset, clock and system controller interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STCOM clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power supply scheme - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply scheme - PLC AFE and line driver section. . . . . . . . . . . . . . . . . . . . . . . . . . 26
TQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Line driver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TQFP176 (20 x 20 x 1 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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STCOM
Description
Table 1. Cortex™-M4F core configuration
Component
Presence
Comment
JTAG
Yes Full-featured debug access port (DAP), SWJ-DP and AHB access port
ETM
ITM
TPIU
FPB
Yes
Yes
Yes
Yes
Embedded Trace Macrocell present
Instrumentation Trace Macrocell
Trace port unit interface present
Flash patch breakpoint
DWT
Yes
Data watchpoint and trace
DEBUG level
IRQ
Priority level
MPU
N/A
N/A
N/A
Yes
Full debug with data matching for watchpoint generation
80 IRQ source
Set to 5:32 levels
Memory protection unit present. 8 regions implemented
FPU
BB
RESET_ALL_REGS
CLKGATE
Yes
Yes
Yes
Yes
Floating point unit present (single precision)
Bit banding region present
Reset all synchronous state
Possibility to minimize dynamic power dissipation by clock gating
WIC Yes 10 lines: NMI, WWDG, RTC, GPIOs, IPC, DMA, GPT0, SPI0 and USART0
1.3.2
1.3.3
Floating point unit (FPU)
The FPU fully supports single precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between the fixed
point and floating point data formats, and floating point constant instructions.
The FPU provides floating point operations that are compliant with the NSI/IEEE Std 754-
2008 A, IEEE Standard for Binary Floating-point Arithmetic©, referred to as the IEEE 754
Standard.
The FPU contains 32 single precision extension registers, which can also be accessible as
16 double word registers for load, store, and move operations.
Nested vectored interrupt controller (NVIC)
The STCOM embeds a NVIC able to handle 80 maskable interrupts. The software priority
level is configurable in the range of 0 - 31 for each interrupt. A higher level corresponds to
a lower priority, so the level 0 is the highest interrupt priority. In case two or more interrupt
lines share the same software priority level, the hardware priority level, which is described in
Table 2, is used.
DocID028515 Rev 1
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STCOM.PDF ] | |
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