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What is 8T49N242?

This electronic component, produced by the manufacturer "Integrated Device Technology", performs the same function as "NG Universal Frequency Translator".


8T49N242 Datasheet PDF - Integrated Device Technology

Part Number 8T49N242
Description NG Universal Frequency Translator
Manufacturers Integrated Device Technology 
Logo Integrated Device Technology Logo 


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FemtoClock® NG Universal Frequency
Translator
8T49N242
Datasheet
General Description
The 8T49N242 has one fractional-feedback PLL that can be used as
a jitter attenuator and frequency translator. It is equipped with four
integer output dividers, allowing the generation of up to four different
output frequencies, ranging from 8kHz to 1GHz. These frequencies
are completely independent of the input reference frequencies and
the crystal reference frequency. The device places virtually no
constraints on input to output frequency conversion, supporting all
FEC rates, including the new revision of ITU-T Recommendation
G.709 (2009), most with 0ppm conversion error. The outputs may
select among LVPECL, LVDS, HCSL or LVCMOS output levels.
This makes it ideal to be used in any frequency synthesis application,
including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and
SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The 8T49N242 accepts up to two differential or single-ended input
clocks and a fundamental-mode crystal input. The internal PLL can
lock to either of the input reference clocks or just to the crystal to
behave as a frequency synthesizer. The PLL can use the second
input for redundant backup of the primary input reference, but in this
case, both input clock references must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS), and generates an alarm when an input clock failure is
detected. Automatic and manual hitless reference switching options
are supported. LOS behavior can be set to support gapped or
un-gapped clocks.
The 8T49N242 supports holdover. The holdover has an initial
accuracy of ±50ppB from the point where the loss of all applicable
input reference(s) has been detected. It maintains a historical
average operating point for the PLL that may be returned to in
holdover at a limited phase slope.
The PLL has a register-selectable loop bandwidth from 0.2Hz to
6.4kHz.
The device supports Output Enable & Clock Select inputs and Lock,
Holdover & LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Programming with IDT’s Timing Commander software is
recommended for optimal device performance. Factory
pre-programmed devices are also available.
Applications
• OTN or SONET / SDH equipment
• Gigabit and Terabit IP switches / routers including Synchronous
Ethernet
• Video broadcast
Features
• Supports SDH/SONET and Synchronous Ethernet clocks including
all FEC rate conversions
• 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz
• Operating Modes: Synthesizer, Jitter Attenuator
• Operates from a 10MHz to 50MHz fundamental-mode crystal or a
10MHz to 125MHz external oscillator
• Initial holdover accuracy of +50ppb.
• Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks
• Accepts frequencies ranging from 8kHz to 875MHz
• Auto and manual clock selection with hitless switching
• Clock input monitoring including support for gapped clocks
• Phase-slope limiting and fully hitless switching options to control
output clock phase transients
• Generates four LVPECL / LVDS / HCSL or eight LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz
(differential)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• Integer divider ranging from ÷4 to ÷786,420 for each output
• Programmable loop bandwidth settings from 0.2Hz to 6.4kHz
• Optional fast-lock function
• Four General Purpose I/O pins with optional support for status &
control:
• Two Output Enable control inputs provide control over the four
clocks
• Manual clock selection control input
• Lock, Holdover and Loss-of-Signal alarm outputs
• Open-drain Interrupt pin
• Register programmable through I2C or via external I2C EEPROM
• Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs,
GPIO and control pins
• -40°C to 85°C ambient operating temperature
• Package: 40QFN, lead-free (RoHS 6)
©2016 Integrated Device Technology, Inc.
1
REVISION 6, November 1, 2016

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8T49N242 equivalent
8T49N242 Datasheet
Number
32
33
34
35
Name
VCCA
OSCI
OSCO
nWP
Type1
Power
I
O
I Pullup
Description
Analog function supply for core analog functions. 2.5V or 3.3V supported.
Crystal Input. Accepts a 10MHz – 50MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal. For proper device
functionality, a crystal or external oscillator must be connected to this pin.
Crystal Output. This pin must be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
Write Protect input. LVTTL / LVCMOS interface levels.
0 = Write operations on the serial port will complete normally, but will have no
effect except on interrupt registers.
36
VCCCS
Power
Output supply for Control & Status pins:
GPIO[3:0], SDATA, SCLK, S_A1, S_A0, nINT, nWP, nRST
1.8V, 2.5V or 3.3V supported
37
CAP
Analog
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
38
CAP_REF
Analog
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
39
40
ePAD
VCCA
S_A0
Exposed Pad
Power
I
Power
Pulldown
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
I2C Address Bit A0.
Negative supply voltage. All VEE pins and ePAD must be connected before any
positive supply voltage is applied.
NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics, VCC = VCCOX = 3.3V±5% or 2.5V±5%1
Symbol
CIN
RPULLUP
Parameter
Input Capacitance2
Input Pullup
Resistor
GPIO[3:0],
nRST, nWP,
SDATA, SCLK
Test Conditions
Input Pulldown
RPULLDOWN Resistor
S_A0, S_A1
LVCMOS
VCCOX = 3.465V
Power Dissipation LVCMOS
VCCOX = 2.625V
CPD
Capacitance
LVCMOS
VCCOX = 1.89V
(per output pair)
LVDS, HCSL or
LVPECL
VCCOX = 3.465V or 2.625V
ROUT
Output
Impedance
GPIO[3:0]
LVCMOS
Q[3:0], nQ[3:0]
VCCCS = 3.3V
VCCCS = 2.5V
VCCCS = 1.8V
VCCOX = 3.3V
VCCOX = 2.5V
VCCOX = 1.8V
NOTE 1: VCCOX denotes: VCCO0, VCCO1, VCCO2 or VCCO3.
NOTE 2: This specification does not apply to the OSCI or OSCO pins.
Minimum
Typical
3.5
Maximum Units
pF
51 k
51 k
11.5 pF
10.5 pF
11 pF
2.5 pF
26
30
42
18
22
30
©2016 Integrated Device Technology, Inc.
5
Revision 6, November 1, 2016


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Featured Datasheets

Part NumberDescriptionMFRS
8T49N241The function is NG Universal Frequency Translator. Integrated Device TechnologyIntegrated Device Technology
8T49N242The function is NG Universal Frequency Translator. Integrated Device TechnologyIntegrated Device Technology

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