PDF SI3454 Data sheet ( Hoja de datos )

Número de pieza	SI3454
Descripción	QUAD IEEE 802.3AT POE PSE CONTROLLER
Fabricantes	Silicon Laboratories
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Si3454 QUAD IEEE 802.3AT POE PSE CONTROLLER Features  Quad-Port Power Sourcing Equipment (PSE) controller  IEEE 802.3at Type I and II compliant  Port priority shutdown control  Adds enhanced features for maximum design flexibility: Per-port current and voltage monitoring PoE Plus support with programmable current limits Multi-point detection Programmable power MOSFET gate drive control Configurable watchdog timer enables failsafe operation  Maskable interrupt pin  Comprehensive fault protection circuitry includes: Power undervoltage lockout Output current limit and short- circuit protection Thermal overload detection  Supports pin-selectable AUTO mode  Extended operating temp range: –40 to +85 °C  5x7 mm 38-pin QFN package (RoHS-compliant)  On-chip dc-dc converter enables single-rail power operation Applications  IEEE Power Sourcing Equipment  IP Phone Systems (PSE)  Smartgrid Switches  Power over Ethernet (PoE) Switches  Ruggedized and Industrial Switches Description The Si3454 is a fully-programmable, four-port power management controller for IEEE 802.3 compliant Power Sourcing Equipment (PSE). Designed for use in PSE endpoint (switches), the Si3454 integrates four independent ports, each with IEEE-required powered device (PD) detection and classification functionality. In addition, the Si3454 features a fully-programmable architecture that enables powered device (PD) disconnect using a dc sense algorithm, a robust multipoint detection algorithm, software-configurable per-port current and voltage monitoring, and programmable current limits to support the IEEE 802.3at standard. Intelligent protection circuitry includes input undervoltage detection, output current limit, and short-circuit protection. The Si3454 operates by host processor control through a three-wire, I2C-compatible serial interface. Independent serial data input and output pins enable high- voltage isolation through external isolators. An interrupt pin is used to alert the host processor of various status and fault conditions. The device also supports a pin-selectable AUTO mode for autonomous operation, without the need for a host processor. The Si3454 also features an on- chip dc-dc converter for creating the digital voltage rail from the PoE voltage, thus enabling single-rail power operation. Ordering Information: See page 49. Rev. 1.1 9/15 Copyright © 2015 by Silicon Laboratories Si3454 1 page Si3454 Table 1. PSE Port Interface Recommended Operating Conditions1 (Continued) Parameter Symbol Test Condition Min Typ Max Unit Power Supply Currents3 VPWR Supply Current VDD Supply Current Detection Specification IVPWR IDD During normal operation —2 5 mA — 18 25 mA Detection Voltage when RDET = 25.5k VPORTn Primary detection voltage — –4.0 –2.8 V Secondary detection voltage –10 –8.0 — V Detection Current Limit Minimum Signature Resistance @ PD IDET Measured when VPORTn = 0 V — 3 4.9 mA RDET_MIN 15 — 19 k Maximum Signature Resistance @ PD RDET_MAX 26.5 — 33 k Shorted Port Threshold Open Port Threshold Classification Specifications RSHORT ROPEN 150 — 400  100 — 400 k Classification Voltage Classification Current VCLASS ICLASS 0 mA < ICLASS < 45 mA –20.5 — –15.5 V Measured when VPORTn = 0 V 55 — 95 mA Class 0 0 — 5 mA Class 1 8 — 13 mA Classification Current Region ICLASS_REGION Class 2 Class 3 16 — 21 mA 25 — 31 mA Class 4 35 — 45 mA Notes: 1. Port voltages are referenced with respect to VPWR. All other voltages are referenced with respect to GND. These specifications apply over the recommended operating voltage and temperature ranges of the device unless noted otherwise. Typical performance is for TA = 25 °C, VDD = AGND + 3.3 V, AGND and DGND = 0 V, and VPWR at 48 V. 2. For a description of the detailed behavior of VDD UVLO, see “4.2.2. Global Event Register and Global Event COR (0x02, 0x03)” . 3. Positive values indicate currents flowing into the device; negative currents indicate current flowing out of the device. Rev. 1.1 5 5 Page Si3454 Table 5. I2C Bus Timing Specifications1,2,3,4,5,6 Parameter Symbol Test Condition Min Typ Max Unit Serial Bus Clock Frequency SCL High Time SCL Low Time Bus Free Time fSCL tSKH tSKL tBUF See Figure 5 0 — 800 kHz See Figure 5 300 — — ns See Figure 5 650 — — ns Between STOP and START con- ditions. See Figure 5 650 — — ns Start Hold Time tSTH Between START and first low SCL. See Figure 5 300 — — ns Start Setup Time tSTS Between SCL high and START condition. See Figure 5 300 — — ns Stop Setup Time Data Hold Time Data Setup Time Time from Hardware or Soft- ware Reset until Start of I2C Traffic tSPS tDH tDS tRESET Between SCL high and STOP condition. See Figure 5 300 — — ns See Figure 57 75 — — ns See Figure 5 100 — — ns Reset to start condition 5 — — ms Notes: 1. All specification voltages are referenced with respect to AGND and DGND at ground. Currents are defined as positive flowing into a pin and negative flowing out of a pin. 2. Not production tested (guaranteed by design). 3. All timing references measured at VIL and VIH. 4. SDAI must be low within ½ SCL clock cycle of SDAO going low for the following reasons: a.) During a read transaction, if the Si3454 is letting SDAO go high and another device is driving SDAO low, this should be recognized as bus contention, and the Si3454 should release the bus. If SDAO low is not present on SDAI within ½ clock cycle, the Si3454 will not recognize this as bus contention and will not release the bus. b.) During any I2C transaction, the Si3454 will ACK (SDAO low) when its address is sent. The Si3454 “expects” that SDAI will follow within ½ of the SCL clock cycle. If SDAI is not low, the Si3454 will release the bus. 5. SCL and SDA rise and fall times depend on bus pullup resistance and bus capacitance. 6. The time from a fault event to the INT pin being driven is software-defined. The Si3454 produces a new measurement result for the Port voltage or current every 3 msec and every 6 msec for the power supplies and temperature. After each port is monitored, the port status, port event registers, INT register, and INT pin are updated in sequence. For this reason, the INT pin can lag the contents of the event registers by approximately 5 ms. 7. 250 ns minimum and 350 ns maximum for the case where the Si3454 is transmitting data. Rev. 1.1 11 11 Page

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