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PDF SI512 Data sheet ( Hoja de datos )
| Número de pieza | SI512 | |
| Descripción | DUAL FREQUENCY CRYSTAL OSCILLATOR | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si512/513
DUAL FREQUENCY CRYSTAL OSCILLATOR (XO)
100 kHZ TO 250 MHZ
Features
Supports any frequency from
3.3, 2.5, or 1.8 V operation
100 kHz to 250 MHz
Differential (LVPECL, LVDS,
Two selectable output frequencies HCSL) or CMOS output options
Low-jitter operation
Optional integrated 1:2 CMOS
2 to 4 week lead times
fanout buffer
Total stability includes 10-year
aging
Runt suppression on OE and
power on
Comprehensive production test Industry standard 5x7 and
coverage includes crystal ESR and 3.2x5 mm packages
DLD
Pb-free, RoHS compliant
On-chip LDO regulator for power
supply noise filtering
–40 to 85 oC operation
Applications
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
Description
Broadcast video
Switches/routers
Telecom
FPGA/ASIC clock generation
The Si512/513 dual frequency XO utilizes Silicon Laboratories' advanced
PLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a
traditional XO where a different crystal is required for each output frequency,
the Si512/513 uses one fixed crystal and Silicon Labs’ proprietary any-
frequency synthesizer to generate any frequency across this range. This IC-
based approach allows the crystal resonator to provide enhanced reliability,
improved mechanical robustness, and excellent stability. In addition, this
solution provides superior supply noise rejection, simplifying low jitter clock
generation in noisy environments. The Si512/513 is factory-configurable for a
wide variety of user specifications, including frequency, supply voltage,
output format, output enable polarity, and stability. Specific configurations are
factory-programmed at time of shipment, eliminating long lead times and
non-recurring engineering charges associated with custom frequency
oscillators.
Functional Block Diagram
VDD
OE
Power Supply Filtering
Fixed
Frequency
Oscillator
Any-Frequency
0.1 to 250 MHz
DSPLL® Synthesis
CLK+
CLK–
Si5602
Ordering Information:
See page 13.
Pin Assignments:
See page 12.
FS 1
6 VDD
OE 2
5 NC
GND 3
4 CLK
Si512 CMOS Dual XO
OE 1
FS 2
GND 3
6 VDD
5 NC
4 CLK
Si513 CMOS Dual XO
FS 1
6 VDD
OE 2
5 CLK–
GND 3
4 CLK+
Si512 LVDS/LVPECL/HCSL/CMOS
Dual XO
OE 1
6 VDD
FS 2
5 CLK–
GND 3
4 CLK+
Si513 LVDS/LVPECL/HCSL/CMOS
Dual XO
Rev. 1.0 5/12
FS GND
Copyright © 2012 by Silicon Laboratories
Si512/13
1 page  
Si512/513
Table 2. Output Clock Frequency Characteristics
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min Typ Max Units
Nominal Frequency
FO
CMOS, Dual CMOS
0.1 — 212.5 MHz
FO LVDS/LVPECL/HCSL
0.1 — 250 MHz
Total Stability*
Frequency Stability Grade C
–30
+30 ppm
Frequency Stability Grade B
–50
+50 ppm
Frequency Stability Grade A
–100
+100 ppm
Temperature Stability
Frequency Stability Grade C
–20
+20 ppm
Frequency Stability Grade B
–25
+25 ppm
Frequency Stability Grade A
–50
+50 ppm
Startup Time
TSU Minimum VDD to output
— — 10 ms
frequency (FO) within specification
Disable Time
TD
FO 10 MHz
——
5 µs
FO < 10 MHz
— — 40 µs
Enable Time
TE
FO 10 MHz
— — 20 µs
FO < 10 MHz
— — 60 µs
Settling Time after FS
Change
tFRQ
— — 10 ms
*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and
vibration (not under operation), and 10 years aging at 40 °C.
Rev. 1.0
5
5 Page 
Si512/513
2. Pin Descriptions
FS 1
6 VDD
OE 2
5 NC
GND 3
4 CLK
Si512 CMOS
OE 1
6 VDD
FS 2
5 NC
GND 3
4 CLK
Si513 CMOS
FS 1
6 VDD
OE 2
5 CLK–
GND 3
4 CLK+
Si512 LVDS/LVPECL/
HCSL/ Dual CMOS*
OE 1
6 VDD
FS 2
5 CLK–
GND 3
4 CLK+
Si513 LVDS/LVPECL/
HCSL/Dual CMOS*
*Note: Supports integrated 1:2 CMOS buffer. See section 2.1 “2.1. Dual CMOS Buffer” and section 3 “3. Ordering Information”.
Table 11. Si512 Pin Descriptions (CMOS, OE Pin 2)
Pin Name
CMOS Function
1 FS Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
2 OE Output Enable. Internal pull-up for OE active high. Pull-
down for OE active low. See ordering information.
3
GND
Electrical and Case Ground.
4 CLK Clock Output.
5 NC No connect. Make no external connection to this pin.
6 VDD Power Supply Voltage.
Table 12. Si513 Pin Descriptions (CMOS, OE Pin 1)
Pin Name
CMOS Function
1 OE Output Enable. Internal pull-up for OE active high. Pull-
down for OE active low. See ordering information.
2 FS Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
3
GND
Electrical and Case Ground.
4 CLK Clock Output.
5 NC No connect. Make no external connection to this pin.
6 VDD Power Supply Voltage.
Table 13. Si512 Pin Descriptions (OE Pin 2)
Pin Name
LVPECL/LVDS/HCSL/Dual CMOS Function
1 FS Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
2 OE Output Enable. Internal pull-up for OE active high. Pull-
down for OE active low. See ordering information.
3
GND
Electrical and Case Ground.
4
CLK+
Clock Output.
5
CLK–
Complementary Clock Output.
6 VDD Power Supply Voltage.
Rev. 1.0
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet SI512.PDF ] | |
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