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PDF F59L1G81MA Data sheet ( Hoja de datos )
| Número de pieza | F59L1G81MA | |
| Descripción | 1 Gbit (128M x 8) 3.3V NAND Flash Memory | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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ESMT
Flash
FEATURES
z Voltage Supply: 3.3V (2.7V~3.6V)
z Organization
- Memory Cell Array: (128M + 4M) x 8bit
- Data Register: (2K + 64) x 8bit
z Automatic Program and Erase
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
z Page Read Operation
- Page Size: (2K + 64) Byte
- Random Read: 25us (Max.)
- Serial Access: 25ns (Min.) (3.3V)
z Memory Cell: 1bit/Memory Cell
z Fast Write Cycle Time
- Program time: 350us - typical
- Block Erase time: 3.5ms - typical
z Command/Address/Data Multiplexed I/O Port
z Hardware Data Protection
- Program/Erase Lockout During Power Transitions
F59L1G81MA (2Y)
Operation Temperature Condition -40°C~85°C
1 Gbit (128M x 8)
3.3V NAND Flash Memory
z Reliable CMOS Floating Gate Technology
- ECC Requirement: - 4bit/512Byte,
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
z Command Register Operation
z Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
z NOP: 4 cycles
z Cache Program Operation for High Performance Program
z Cache Read Operation
z Copy-Back Operation
z EDO mode
z OTP Operation
z Bad-Block-Protect
ORDERING INFORMATION
Product ID
F59L1G81MA -25TIG2Y
F59L1G81MA -25BIG2Y
F59L1G81MA -25BCIG2Y
Speed
25 ns
25 ns
25 ns
Package
48 pin TSOPI
63 ball BGA
67 ball BGA
Comments
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The device is a 128Mx8bit with spare 4Mx8bit capacity. The
device is offered in 3.3V Vcc Power Supply. Its NAND cell
provides the most cost-effective solution for the solid state mass
storage market. The memory is divided into blocks that can be
erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 1024 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 2,112-Byte page in
typical 350us and an erase operation can be performed in typical
3.5ms on a 128K-Byte for X8 device block.
Data in the page mode can be read out at 25ns cycle time per
Byte. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2014
Revision: 1.1
1/44
1 page  
ESMT
BLOCK DIAGRAM
F59L1G81MA (2Y)
Operation Temperature Condition -40°C~85°C
ARRAY ORGANIZATION
Array Address
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6
1st cycle A0 A1 A2 A3 A4 A5 A6
2nd cycle A8
A9 A10 A11
L*
L*
L*
3rd cycle A12 A13 A14 A15 A16 A17 A18
4th cycle A20 A21 A22 A23 A24 A25 A26
Note:
1. Column Address: Starting Address of the Register.
2. *L must be set to “Low”.
3. The device ignores any additional input of address cycles than required.
I/O7 Address
A7 Column Address
L* Column Address
A19 Row Address
A27 Row Address
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2014
Revision: 1.1
5/44
5 Page 
ESMT
F59L1G81MA (2Y)
Operation Temperature Condition -40°C~85°C
NAND Flash Technical Notes
Mask Out Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by ESMT. The
information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the
same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not
affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The
system design must be able to mask out the initial invalid block(s) via address mapping.
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 4bit/512Byte
ECC.
Identifying Initial Invalid Block(s) and Block Replacement Management
All device locations are erased (FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial
invalid block(s) status is defined by the 1st byte in the spare area. ESMT makes sure that either the 1st or 2nd page of every initial
invalid block has non-FFh data at the 1st byte column address in the spare area.
Do not erase or program factory-marked bad blocks. The host controller must be able to recognize the initial invalid block information
and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop
with Flash memory usage.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2014
Revision: 1.1
11/44
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