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PDF F59D2G161A Data sheet ( Hoja de datos )
| Número de pieza | F59D2G161A | |
| Descripción | 2 Gbit (256M x 8 / 128M x 16) 1.8V NAND Flash Memory | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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ESMT
Flash
FEATURES
Voltage Supply: 1.8V (1.7V ~ 1.95V)
Organization
x8:
- Memory Cell Array: (256M + 8M) x 8bit
- Data Register: (2K + 64) x 8bit
x16:
- Memory Cell Array: (128M + 4M) x 16bit
- Data Register: (1K + 32) x 16bit
Automatic Program and Erase
x8:
- Page Program: (2K + 64) byte
- Block Erase: (128K + 4K) byte
x16:
- Page Program: (1K + 32) word
- Block Erase: (64K + 2K) word
Page Read Operation
- Page Size: (2K + 64) Byte (x8)
Page Size: (1K + 32) Word (x16)
- Random Read: 25us (Max.)
- Serial Access: 45ns (Min.)
Memory Cell: 1bit/Memory Cell
Fast Write Cycle Time
- Program time: 350us (Typ.)
- Block Erase time: 3.5ms (Typ.)
F59D2G81A / F59D2G161A
2 Gbit (256M x 8 / 128M x 16)
1.8V NAND Flash Memory
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
- ECC Requirement: x8 - 4bit/512Byte
x16 - 4bit/256 Word
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
Command Register Operation
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
NOP: 4 cycles
Cache Program/Read Operation
Copy-Back Operation
Two-Plane Operation
EDO mode
Bad-Block-Protect
ORDERING INFORMATION
Product ID
Speed
Package
x8:
F59D2G81A -45TG
45 ns
48 pin TSOPI
F59D2G81A -45BG
x16:
45 ns
63 ball BGA
F59D2G161A -45BG 45 ns
63 ball BGA
Comments
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The device is a 256Mx8bit with spare 8Mx8bit capacity (or
128Mx16bit with spare 4Mx16bit capacity). The device is offered
in 1.8V VCC Power Supply. Its NAND cell provides the most
cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased
independently so it is possible to preserve valid data while old
data is erased.
The device contains 2048 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 1056-Word page in
typical 350us and an erase operation can be performed in typical
3.5ms on a 128K-Byte for X8 device block (or 64K-Word for X16
device block).
Data in the page mode can be read out at 45ns cycle time per
Elite Semiconductor Memory Technology Inc.
Word. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Publication Date: May 2014
Revision: 1.4
1/56
1 page  
ESMT
BLOCK DIAGRAM (x8)
F59D2G81A / F59D2G161A
ARRAY ORGANIZATION (x8)
Array Address (x8)
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6
1st cycle A0 A1 A2 A3 A4 A5 A6
2nd cycle A8
A9 A10 A11
L*
L*
L*
3rd cycle A12 A13 A14 A15 A16 A17 A18
4th cycle A20 A21 A22 A23 A24 A25 A26
5th cycle A28
L*
L*
L*
L*
L*
L*
NOTE:
Column Address: Starting Address of the Register.
*L must be set to “Low”.
* The device ignores any additional input of address cycles than required.
A18 is for Plane Address setting.
I/O7
A7
L*
A19
A27
L*
Address
Column Address
Column Address
Row Address
Row Address
Row Address
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.4
5/56
5 Page 
ESMT
F59D2G81A / F59D2G161A
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay
CLE to RE Delay
Ready to RE Low
RE Pulse Width
WE High to Busy
Symbol
tR
tAR
tCLR
tRR
tRP
tWB
Min.
-
10
10
20
25
-
Max.
25
-
-
-
-
100
WP Low to WE Low (disable mode)
WP High to WE Low (enable mode)
Read Cycle Time
RE Access Time
tWW
tRC
tREA
100
45
-
-
-
30
CE Access Time
tCEA
-
45
RE High to Output Hi-Z
tRHZ
-
100
CE High to Output Hi-Z
tCHZ
-
30
CE High to ALE or CLE Don’t Care
tCSD
0
-
RE High to Output Hold
RE Low to Output Hold
tRHOH
tRLOH
15
5
-
-
CE High to Output Hold
tCOH
15
-
RE High Hold Time
tREH
15
-
Output Hi-Z to RE Low
tIR 0
-
RE High to WE Low
tRHW
100
-
WE High to RE Low
Read
Device Resetting
Program
Time during ...
Erase
Ready
Cache Busy in Read Cache (following
31h and 3Fh)
tWHR
tRST
tDCBSYR
60
-
-
-
-
-
-
5
10
500
5(1)
30
NOTE: 1. If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
Unit
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
us
us
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.4
11/56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet F59D2G161A.PDF ] | |
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