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PDF F25L16PA Data sheet ( Hoja de datos )

Número de pieza F25L16PA
Descripción 16 Mbit Serial Flash Memory
Fabricantes Elite Semiconductor 
Logotipo Elite Semiconductor Logotipo



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ESMT
Flash
F25L16PA (2S)
16 Mbit Serial Flash Memory
with Dual
„ FEATURES
y Single supply voltage 2.7~3.6V
y Standard and Dual
y Speed
- Read max frequency: 50MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz / 100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI)
y Low power consumption
- Active current: 23.5 mA (max.)
- Standby current: 25 μ A (max.)
- Deep Power Down current: 10 μ A (max.)
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Page programming time: 1.5 ms (typical)
y Erase
- Chip Erase time 10 sec (typical)
- 64K bytes Block Erase time 1 sec (typical)
- 32K bytes Block Erase time 500 ms (typical)
- 4K bytes Sector Erase time 120 ms (typical)
y Page Programming
- 256 byte per programmable page
y Lockable 512 bytes OTP security sector
y SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y All Pb-free products are RoHS-Compliant
„ ORDERING INFORMATION
Product ID
Speed
F25L16PA –50PG2S
50MHz
F25L16PA –86PG2S
86MHz
F25L16PA –100PG2S 100MHz
F25L16PA –50PAG2S 50MHz
F25L16PA –86PAG2S 86MHz
F25L16PA –100PAG2S 100MHz
F25L16PA –50PHG2S 50MHz
F25L16PA –86PHG2S 86MHz
F25L16PA –100PHG2S 100MHz
F25L16PA –50DG2S
50MHz
F25L16PA –86DG2S
86MHz
F25L16PA –100DG2S 100MHz
F25L16PA –50HG2S
50MHz
F25L16PA –86HG2S
86MHz
F25L16PA –100HG2S 100MHz
Package
Comments
8-lead
SOIC
150 mil
Pb-free
8-lead
SOIC
200 mil
Pb-free
16-lead
SOIC
300 mil
Pb-free
8-pin
PDIP
300 mil
Pb-free
8-contact
WSON
6x5 mm
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
1/42

1 page




F25L16PA pdf
ESMT
F25L16PA (2S)
„ PIN DESCRIPTION
Symbol
SCK
SI / SIO0
SO / SIO1
CE
WP
HOLD
VDD
VSS
Pin Name
Serial Clock
Serial Data Input /
Serial Data Input Output 0
Serial Data Output /
Serial Data Input Output 1
Chip Enable
Write Protect
Hold
Power Supply
Ground
Functions
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO
pin to transfer commands, addresses or data serially into the device on the
rising edge of SCK and read data or status from the device on the falling edge
of SCK(for Dual mode).
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual mode).
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status
register.
To temporality stop serial communication with SPI flash memory without
resetting the device.
To provide power.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
5/42

5 Page





F25L16PA arduino
ESMT
F25L16PA (2S)
„ STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Bit Name
Function
Status Register
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
2 BP0 Indicate current level of block write protection (See Table 3)
3 BP1 Indicate current level of block write protection (See Table 3)
4 BP2 Indicate current level of block write protection (See Table 3)
5 BP3 Indicate current level of block write protection (See Table 3)
6 RESERVED Reserved for future use
7
BPL
1 = BP3, BP2,BP1,BP0 are read-only bits
0 = BP3, BP2,BP1,BP0 are read/writable
Note:
1. BUSY and WEL are read only.
2. BP0~3 and BPL bits are non-volatile.
Default at
Power-up
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
N/A
R/W
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Page Program instruction completion
Sector Erase instruction completion
Block Erase instruction completion
Chip Erase instruction completion
Write Status Register instructions
BUSY
The BUSY bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the BUSY bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
11/42

11 Page







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