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PDF SIS892ADN Data sheet ( Hoja de datos )
| Número de pieza | SIS892ADN | |
| Descripción | N-Channel 100-V (D-S) MOSFET | |
| Fabricantes | Vishay | |
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N-Channel 100 V (D-S) MOSFET
SiS892ADN
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
100
RDS(on) () (Max.)
0.033 at VGS = 10 V
0.036 at VGS = 7.5 V
0.047 at VGS = 4.5 V
ID (A)f
28
26.8
23.5
Qg (Typ.)
6.1 nC
FEATURES
• TrenchFET® Power MOSFET
• 100 % Rg and UIS Tested
• Capable of Operating with 5 V Gate Drive
• Material categorization: For definitions of
compliance please see www.vishay.com/doc?99912
PowerPAK® 1212-8
3.30 mm
S
1S
3.30 mm
2
S
3G
4
D
8D
7
D
6
D
5
Bottom View
Ordering Information:
SiS892ADN-T1-GE3 (Lead (Pb)-free and Halogen-free)
APPLICATIONS
• Telecom Bricks
• Primary side switch
• Synchronous Rectification
• Industrial
D
G
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
TC = 70 °C
TA = 25 °C
ID
Pulsed Drain Current (t = 300 µs)
TA = 70 °C
IDM
Continuous Source-Drain Diode Current
TC = 25 °C
TA = 25 °C
IS
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
L = 0.1 mH
IAS
EAS
TC = 25 °C
Maximum Power Dissipation
TC = 70 °C
TA = 25 °C
PD
TA = 70 °C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)c, d
TJ, Tstg
Limit
100
± 20
28
22.3
7.4a, b
6.0a, b
40
30g
3.1a, b
10
5
52
33
3.7a, b
2.4a, b
- 55 to 150
260
Unit
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambienta, e
Maximum Junction-to-Case (Drain)
t 10 s
Steady State
RthJA
RthJC
28
2.0
34
°C/W
2.4
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Maximum under steady state conditions is 81 °C/W.
f. Based on TC = 25 °C.
g. Package limited.
Document Number: 62716
For technical questions, contact: [email protected]
www.vishay.com
S12-1259-Rev. A, 21-May-12
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1 page  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
40
SiS892ADN
Vishay Siliconix
32
24
16
8
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Current Derating*
65 2.0
52 1.6
39 1.2
26 0.8
13 0.4
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power, Junction-to-Case
0.0
0
25 50 75 100 125
TA - Ambient Temperature (°C)
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 62716
For technical questions, contact: [email protected]
www.vishay.com
S12-1259-Rev. A, 21-May-12
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
5 Page 
AN822
Vishay Siliconix
105
Spreading Copper (sq. in.)
95
85
75
65
55
0%
45
100 %
50 %
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. Spreading Copper - Si7401DN
130
120 Spreading Copper (sq. in.)
110
100
90
80
50 %
100 %
70
60 0 %
50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal perfor-
mance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attrac-
tive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOS-
FET die in the standard TSSOP-8 or SO-8 packages.
www.vishay.com
4
Document Number 71681
03-Mar-06
11 Page | ||
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