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SIS892DN PDF Datasheet - N-Channel 100-V (D-S) MOSFET - Vishay

Part Number SIS892DN
Description N-Channel 100-V (D-S) MOSFET
Manufacturers Vishay 
Logo Vishay Logo 
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SIS892DN datasheet, circuit
N-Channel 100 V (D-S) MOSFET
SiS892DN
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
100
RDS(on) ()
0.029 at VGS = 10 V
0.042 at VGS = 4.5 V
PowerPAK 1212-8
ID (A)f
30g
25
Qg (Typ.)
6.7 nC
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• 100 % UIS Tested
• Compliant to RoHS Directive 2002/95/EC
3.30 mm
D
8D
7
D
6
D
5
S
1S
3.30 mm
2
S
3G
4
Bottom View
APPLICATIONS
• DC/DC Primary Side Switch
• Telecom/Server 48 V
• DC/DC Converter
G
D
S
Ordering Information: SiS892DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
Gate-Source Voltage
TC = 25 °C
VDS
VGS
Continuous Drain Current (TJ = 150 °C)
Pulsed Drain Current
Continuous Source-Drain Diode Current
TC = 70 °C
TA = 25 °C
TA = 70 °C
TC = 25 °C
TA = 25 °C
ID
IDM
IS
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
L = 0.1 mH
IAS
EAS
Maximum Power Dissipation
TC = 25 °C
TC = 70 °C
TA = 25 °C
PD
TA = 70 °C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)c, d
TJ, Tstg
Limit
100
± 20
30g
27
8.0a, b
7.3a, b
50
30g
3.1a, b
10
5
52
43
3.7a, b
3.1a, b
- 55 to 150
260
N-Channel MOSFET
Unit
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambienta, e
Maximum Junction-to-Case (Drain)
t 10 s
Steady State
RthJA
RthJC
26
1.9
33
°C/W
2.4
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. See solder profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Maximum under steady state conditions is 81 °C/W.
f. Based on TC = 25 °C.
g. Package limited.
Document Number: 66590
S10-2682-Rev. B, 22-Nov-10
www.vishay.com
1

1 page

SIS892DN pdf, schematic
SiS892DN
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
On-State Drain Currenta
Drain-Source On-State Resistancea
Forward Transconductancea
Dynamicb
VDS
VDS/TJ
VGS(th)/TJ
VGS(th)
IGSS
IDSS
ID(on)
RDS(on)
gfs
VGS = 0 V, ID = 250 µA
ID = 250 µA
VDS = VGS , ID = 250 µA
VDS = 0 V, VGS = ± 20 V
VDS = 100 V, VGS = 0 V
VDS = 100 V, VGS = 0 V, TJ = 55 °C
VDS 5 V, VGS = 10 V
VGS 10 V, ID = 10 A
VGS 4.5 V, ID = 7 A
VDS = 15 V, ID = 10 A
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Ciss
Coss
Crss
Qg
VDS = 50 V, VGS = 0 V, f = 1 MHz
VDS = 50 V, VGS = 10 V, ID = 10 A
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Qgs
Qgd
Rg
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
Notes:
a. Pulse test; pulse width 300 µs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
VDS = 50 V, VGS = 4.5 V, ID = 10 A
f = 1 MHz
VDD = 50 V, RL = 5
ID 10 A, VGEN = 7.5 V, Rg = 1
VDD = 50 V, RL = 5
ID 10 A, VGEN = 10 V, Rg = 1
TC = 25 °C
IS = 5 A, VGS 0 V
IF = 5 A, dI/dt = 100 A/µs, TJ = 25 °C
Min.
Typ.
Max. Unit
100 V
44
- 5.5
mV/°C
1.2 3.0 V
± 100 nA
1
µA
10
20 A
0.024
0.034
0.029
0.042
22 S
611
404 pF
36
14.2 21.5
6.7 10
nC
1.6
3.6
1.0 5.5 10
10 20
13 26
17 34
8 16
ns
8 16
11 22
21 40
9 18
30
A
50
0.81 1.2
V
32 64 ns
31 62 nC
17
ns
15
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
www.vishay.com
2
Document Number: 66590
S10-2682-Rev. B, 22-Nov-10

2 Page

SIS892DN equivalent
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
35
SiS892DN
Vishay Siliconix
28
21
14
7
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Current Derating*
65 2.0
52 1.6
39 1.2
26 0.8
13 0.4
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power, Junction-to-Case
0.0
0
25 50 75 100 125
TA - Ambient Temperature (°C)
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 66590
S10-2682-Rev. B, 22-Nov-10
www.vishay.com
5

5 Page

SIS892DN diode, scr
AN822
Vishay Siliconix
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
Ramp-Up Rate
Temperature at 155 ± 15 °C
Temperature Above 180 °C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
+ 6 °C /Second Maximum
120 Seconds Maximum
70 - 180 Seconds
240 + 5/- 0 °C
20 - 40 Seconds
+ 6 °C/Second Maximum
Figure 2. Solder Reflow Temperature Profile
140 - 170 °C
3° C/s (max)
210 - 220 °C
3 ° C/s (max)
60 s (min)
Pre-Heating Zone
10 s (max)
183 °C
50 s (max)
Reflow Zone
Maximum peak temperature at 240 °C is allowed.
4 ° C/s (max)
www.vishay.com
2
Figure 3. Solder Reflow Temperatures and Time Durations
Document Number 71681
03-Mar-06

9 Page





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