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SIR882DP PDF Datasheet - Vishay

Part Number SIR882DP
Description N-Channel 100-V (D-S) MOSFET
Manufacturers Vishay 
Logo Vishay Logo 
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SIR882DP datasheet, circuit
New Product
N-Channel 100 V (D-S) MOSFET
SiR882DP
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
0.0087 at VGS = 10 V
100 0.0094 at VGS = 7.5 V
0.0115 at VGS = 4.5 V
PowerPAK® SO-8
ID (A)a
60
60
60
Qg (Typ.)
18.3 nC
6.15 mm
D
8D
7
D
6
D
5
S
1S
5.15 mm
2
S
3G
4
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• 100 % UIS Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• DC/DC Primary Side Switch
• Telecom/Server 48 V, Full/Half-Bridge dc-to-dc
• Industrial
D
G
Bottom View
Ordering Information: SiR882DP-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
TC = 70 °C
TA = 25 °C
ID
TA = 70 °C
Pulsed Drain Current
IDM
Continuous Source-Drain Diode Current
TC = 25 °C
TA = 25 °C
IS
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
L =0.1 mH
IAS
EAS
TC = 25 °C
Maximum Power Dissipation
TC = 70 °C
TA = 25 °C
PD
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d, e
TA = 70 °C
TJ, Tstg
Limit
100
± 20
60a
55
17.6b, c
13.9b, c
80
60a
4.9b, c
30
45
83
53
5.4b, c
3.4b, c
- 55 to 150
260
Unit
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambientb, f
Maximum Junction-to-Case (Drain)
t 10 s
Steady State
RthJA
RthJC
18
1.0
23 °C/W
1.5
Notes:
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See solder profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 65 °C/W.
Document Number: 65932
S10-2681-Rev. B, 22-Nov-10
www.vishay.com
1

1 page
line_dark_gray
SIR882DP pdf, schematic
SiR882DP
Vishay Siliconix
New Product
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
VDS/TJ
VGS(th)/TJ
ID = 250 µA
Gate-Source Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 µA
Gate-Source Leakage
IGSS
VDS = 0 V, VGS = ± 20 V
Zero Gate Voltage Drain Current
IDSS
VDS = 100 V, VGS = 0 V
VDS = 100 V, VGS = 0 V, TJ = 55 °C
On-State Drain Currenta
ID(on)
VDS 5 V, VGS = 10 V
VGS = 10 V, ID = 20 A
Drain-Source On-State Resistancea
RDS(on)
VGS = 7.5 V, ID = 17 A
VGS = 4.5 V, ID = 15 A
Forward Transconductancea
gfs VDS = 10 V, ID = 20 A
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
VDS = 50 V, VGS = 0 V, f = 1 MHz
Reverse Transfer Capacitance
Crss
Total Gate Charge
VDS = 50 V, VGS = 10 V, ID = 20 A
Qg VDS = 50 V, VGS = 7.5 V, ID = 20 A
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
td(on)
Rise Time
tr
Turn-Off Delay Time
td(off)
Fall Time
tf
Turn-On Delay Time
td(on)
Rise Time
tr
Turn-Off Delay Time
td(off)
Fall Time
tf
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
Notes:
a. Pulse test; pulse width 300 µs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
VDS = 50 V, VGS = 4.5 V, ID = 20 A
f = 1 MHz
VDD = 50 V, RL = 5
ID 10 A, VGEN = 10 V, Rg = 1
VDD = 50 V, RL = 5
ID 10 A, VGEN = 7.5 V, Rg = 1
TC = 25 °C
IS = 5 A
IF = 10 A, dI/dt = 100 A/µs, TJ = 25 °C
Min.
Typ.
Max.
Unit
100 V
50
- 5.8
mV/°C
1.2 2.8 V
± 100
nA
1
µA
10
30 A
0.0071 0.0087
0.0076 0.0094
0.0092 0.0115
57 S
1930
1210
pF
65
38.5 58
29 44
18.3 27.5
nC
5.5
7.8
0.4 1.9 3.8
12 24
12 24
36 70
9 18
ns
13 26
15 30
35 70
8 16
0.75
64
80
24
40
60
80
1.1
120
160
A
V
ns
nC
ns
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
www.vishay.com
2
Document Number: 65932
S10-2681-Rev. B, 22-Nov-10

2 Page
line_dark_gray
SIR882DP equivalent
New Product
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
80
SiR882DP
Vishay Siliconix
64
Package Limited
48
32
16
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Current Derating*
100 2.5
80 2.0
60 1.5
40 1.0
20 0.5
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power, Junction-to-Case
0
0 25 50 75 100 125 150
TA - Ambient Temperature (°C)
Power, Junction-to-Ambient
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 65932
S10-2681-Rev. B, 22-Nov-10
www.vishay.com
5

5 Page
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SIR882DP diode, scr
AN821
Vishay Siliconix
PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and the
pin dimensions of the PowerPAK SO-8 dual are the
same as standard SO-8 dual devices. Therefore, the
PowerPAK device connection pads match directly to
those of the SO-8. As in the single-channel package,
the only exception is the extended drain connection
area. Manufacturers can likewise take immediate
advantage of the PowerPAK SO-8 dual devices by
mounting them to existing SO-8 dual land patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK SO-8 dual package.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
ture profile used, and the temperatures and time
duration, are shown in Figures 3 and 4.
For the lead (Pb)-free solder profile, see http://
www.vishay.com/doc?73257.
Ramp-Up Rate
Temperature at 155 ± 15 °C
Temperature Above 180 °C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
+ 6 °C /Second Maximum
120 Seconds Maximum
70 - 180 Seconds
240 + 5/- 0 °C
20 - 40 Seconds
+ 6 °C/Second Maximum
Figure 3. Solder Reflow Temperature Profile
140 - 170 °C
3 °C(max)
210 - 220 °C
3 °C(max)
10 s (max)
183 °C
60 s (min)
Pre-Heating Zone
50 s (max)
Reflow Zone
Maximum peak temperature at 240 °C is allowed.
4 °C/s (max)
Figure 3. Solder Reflow Temperatures and Time Durations
www.vishay.com
2
Document Number 71622
28-Feb-06

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