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PDF IRF530 Data sheet ( Hoja de datos )
| Número de pieza | IRF530 | |
| Descripción | 14A, 100V, Power Field Effect Transistor | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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IRF530
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TMOS E−FET.™
Power Field Effect
Transistor
N−Channel Enhancement−Mode Silicon
Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a drain−to−source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters, and PWM motor controls.
These devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating area are critical and offer
additional safety margin against unexpected voltage transients.
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
http://onsemi.com
TMOS POWER FET
14 AMPERES, 100 VOLTS
RDS(on) = 0.140 W
CASE 221A−09
TO-220AB
D
®
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
Gate−to−Source Voltage — Continuous
Gate−to−Source Voltage — Single Pulse (tp ≤ 50 mS)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 mS)
Total Power Dissipation @ TC = 25°C
Derate above 25°C
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Operating and Storage Temperature Range
TJ, Tstg
UNCLAMPED DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C)
Single Pulse Drain−to−Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 75 V, VGS = 10 V, PEAK IL = 14 A, L = 1.0 mH, RG = 25 W)
EAS
THERMAL CHARACTERISTICS
Thermal Resistance — Junction−to−Case°
Thermal Resistance — Junction−to−Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
E−FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
This document contains information on a product under development. Motorola reserves
the right to change or discontinue this product without notice.
RθJC
RθJA
TL
G
Value
100
100
± 20
± 25
14
10
49
78
0.63
−55 to 150
S
Unit
Vdc
Vdc
Vdc
Vdc
Adc
Apk
Watts
W/°C
°C
mJ
98
1.60 °C/W
62.5
275 °C
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 2
1
Publication Order Number:
IRF530/D
1 page  
IRF530
10 80
9 QT
72
8
7 Q1
VGS
Q2
64
56
6 48
5 40
4 32
3 24
2
1 Q3
VDS
TJ = 25°C 16
ID = 14 A 8
00
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
TJ = 25°C
ID = 8 A
VDD = 36 V
VGS = 10 V
tr
td(off)
10
tf
td(on)
1
1 10 10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
14
VGS = 0 V
12 TJ = 25°C
10
8
6
4
2
0
0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as
shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For
http://onsemi.com
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| PDF Descargar | [ Datasheet IRF530.PDF ] | |
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