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PDF CMX885 Data sheet ( Hoja de datos )
| Número de pieza | CMX885 | |
| Descripción | Marine VHF Audio and Signalling Processor | |
| Fabricantes | Consumer Microcircuits Limited | |
| Logotipo |  |
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CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CMX885
Marine VHF Audio and
Signalling Processor
D/885/3 December 2010
Audio and Signalling Processing, DTMF, DSC/ATIS and NOAA
with Auxiliary Functions for use in Marine VHF Systems
Features
• Concurrent Audio/Signalling/Data Operations
• Complete Audio-band Processing:
o Selectable Audio Processing Order
o Pre and De-emphasis
o Selectable 2.55/3.0 kHz Filtering
o Limiter
• DSC/ATIS Modem for Marine Applications
• Programmable Voice Scrambler
• Inband Signalling: DTMF, NOAA NWR
• C-BUS Serial Interface to Host µController
• DTMF and Audio Tone Encoder/Decoder
• Small VQFN and LQFP Packages
• Dual Auxiliary ADC, 4 Multiplexed Inputs
• 4 x Auxiliary DACs
• Dual Programmable System Clock Outputs
• Tx Outputs for Single, Two-Point Modulation
• 3 x Analogue Inputs (Mic or Discriminator)
• Digital Gain Adjustment
• Default 3.6864MHz Xtal/Clock
• Flexible Powersave Modes
• Low-power 3.0V to 3.6V Operation
Audio Out
Mic Input
Auxiliary
Multiplexed
ADC Inputs
Host µC
IRQ
C-BUS
Reference Clock
3V to 3.6V Supply
System Clock 1
System Clock 2
CMX885
Marine VHF
Baseband Processor
Auxiliary
DACs
Modulator
Discriminator
Optional 2nd Receiver
Discriminator
Tx Enable
Rx Enable
RF
(Rx/Tx)
RF
(Rx)
1 Brief Description
The CMX885 is a half-duplex, audio, signalling and data processing IC for use in Marine VHF radio
systems.
Comprehensive audio processing facilities include complete audio processing, filtering, pre- or de-
emphasis and frequency inversion scrambling. Signal routing and filtering is included to assist host µC
based signal encoding/decoding applications.
1200bps Digital Selcall (DSC) or Automatic Transmitter Identification System (ATIS) modem with protocol
support and NWR decoding are supported.
A DTMF encoder/decoder, a full complement of auxiliary ADCs and DACs and dual synthesised clock
outputs are included in this low power PMR processor. The device also has flexible powersaving modes
and is available in 48-pin VQFN and LQFP packages.
© 2010 CML Microsystems Plc
1 page  
Marine VHF Audio and Signalling Processor
CMX885
1.1 History
Version Changes
Date
3 • Clarified operation of Data End bit (b7) for DSC Rx mode in section 8.1.22.
20/12/201
• Clarified the need for observing C-BUS latency when writing multiple C-BUS
0
commands in section 7.3.
• Minor typographical corrections in table of section 8.1.27, P4.10 and P4.11
values in section 8.2.5.
2 • Changed "Modem Control" to "Modem Cofiguration" register
8/4/2010
• Bit references changed to "$C1:b12" style, for consistency
• Changed name of $C1:b2 to "Modem Enable" and $C!:b4 to "Modem Source"
• Deleted other references to "processing" in the description of $C1 register bits
• Deleted the reference to "clearing the En_DSC bit" at the end of section 7.7.1
• Xtal frequency tolerance in section 9.1.4 changed from 100ppm to 30ppm, to
meet DSC specifications.
• Corrected DAC3 to DAC4 in figure 1.
• +1dB and 3dB limits apply to all Rx and Tx responses (figures 6 to 10).
Wording changed accordingly in section 7.5.
• "write" added to description of Audio Tone register ($CD) in section 7.6.
• Reference in $C1 to bits 11-9 should read 11-8 in section 7.6.
• Program Block registers P3.2 to P3.6 should read P3.2 - P3.7 in section 7.11.1.
• GPIO RXENA and TXENA signals - nomenclature standardised in section 7.12.
• Hyperlink added for $C1 in section 8.1.
• Correction of $C0 b6 to "BIAS Block Enable" in section 8.1.17.
• Merge table rows for $CE b9 in section 8.1.28.
• Removed references to MSK: these should be DSC in sections 7.7.1 and 7.7.2.
• Clarification of Status register bit 3, Modem Control register bits 3-8 and bit 11,
Interrupt Mask register bits 3 and 5.
• Footnotes in Parametric Specifications harmonised with table references.
• Minor typographical corrections.
1 • This document created – based on 7041FI-1.x documentation
18/9/2009
© 2010 CML Microsystems Plc
5
D/885/3
5 Page 
Marine VHF Audio and Signalling Processor
CMX885
Notes:
1. X1 can be a crystal or an external clock generator; this will depend on the application. The tracks
between the crystal and the device pins should be as short as possible to achieve maximum stability
and best start up performance. By default, a 3.6864MHz clock is selected, other values could be
used if the various internal clock dividers are set to appropriate values.
2. R5 should be selected to provide the desired dc gain (assuming C11 is not present) of the DISCN
input, as follows:
⏐GAINDISCN⏐ = 100kΩ / R5
The gain should be such that the resultant output at the DISCFB pin is within the input signal range
specified in 7.13.2.
3. R7 should be selected to provide the desired dc gain (assuming C13 is not present) of the ALTN
input as follows:
⏐GAINALTN⏐ = 100kΩ / R7
The gain should be such that the resultant output at the ALTFB pin is within the input signal range
specified in 7.13.
4. R9 should be selected to provide the desired dc gain (assuming C15 is not present) of the MICN
input as follows:
⏐GAINMICN⏐ = 100kΩ / R9
The gain should be such that the resultant output at the MICFB pin is within the input signal range
specified in 7.13.1. For optimum performance with low signal microphones, an additional external
gain stage may be required.
5. C11, C13 and C15 should be selected to maintain the lower frequency roll-off of the MICN, ALTN
and DISCN inputs as follows:
C11 ≥ 100nF × ⏐GAINDISCN⏐
C13 ≥ 100nF × ⏐GAINALTN⏐
C15 ≥ 30nF × ⏐GAINMICN⏐
6. ALTN and ALTFB connections allow the user to have an additional signal input. Component
connections and values are as for the respective DISCN and MICN networks. If this input is not
required, the ALTN pin should be connected to AVss.
7. C5 (AUDIO output) should be increased to 1.0µF if frequencies below 300Hz need to be used on
this pin.
8. A single 10µF electrolytic capacitor (C24, fitted as shown) may be used for smoothing the power
supply to both VDEC pins, providing they are connected together on the pcb with an adequate width
power supply trace. Alternatively, separate smoothing capacitors should be connected to each
VDEC pin. High frequency decoupling capacitors (C3 and C23) must always be fitted as close as
possible to both VDEC pins.
© 2010 CML Microsystems Plc
11
D/885/3
11 Page | ||
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