74ACT245 Datasheet PDF - Fairchild Semiconductor
Part Number | 74ACT245 | |
Description | Octal Bidirectional Transceiver | |
Manufacturers | Fairchild Semiconductor | |
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January 2008
74AC245, 74ACT245
Octal Bidirectional Transceiver with 3-STATE
Inputs/Outputs
Features
■ ICC and IOZ reduced by 50%
■ Non-inverting buffers
■ Bidirectional data path
■ A and B outputs source/sink 24mA
■ ACT245 has TTL-compatible inputs
General Description
The AC/ACT245 contains eight non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for
bus-oriented applications. Current sinking capability is
24mA at both the A and B ports. The Transmit/Receive
(T/R) input determines the direction of data flow through
the bidirectional transceiver. Transmit (active-HIGH)
enables data from A ports to B ports; Receive (active-
LOW) enables data from B ports to A ports. The Output
Enable input, when HIGH, disables both A and B ports
by placing them in a HIGH Z condition.
Ordering Information
Order Number
Package
Number
Package Description
74AC245SC
74AC245SJ
74AC245MTC
74AC245PC
74ACT245SC
74ACT245SJ
74ACT245MSA
74ACT245MTC
74ACT245PC
M20B
M20D
MTC20
N20A
M20B
M20D
MSA20
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
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![]() ![]() DC Electrical Characteristics for ACT
Symbol
VIH
Parameter
Minimum HIGH Level
Input Voltage
VCC (V)
4.5
5.5
Conditions
VOUT = 0.1V or
VCC − 0.1V
TA = +25°C TA = −40°C to +85°C
Typ. Guaranteed Limits
1.5 2.0
2.0
1.5 2.0
2.0
VIL Maximum LOW
Level Input Voltage
4.5 VOUT = 0.1V or
5.5 VCC − 0.1V
1.5 0.8
1.5 0.8
0.8
0.8
VOH Minimum HIGH Level
Output Voltage
4.5 IOUT = −50µA
5.5
4.49 4.4
5.49 5.4
4.4
5.4
VOL Maximum LOW
Level Output Voltage
4.5 VIN = VIL or VIH,
IOH = −24mA
5.5 VIN = VIL or VIH,
IOH = −24mA(4)
4.5 IOUT = 50µA
5.5
3.86
4.86
0.001
0.001
0.1
0.1
3.76
4.76
0.1
0.1
IIN Maximum Input
Leakage Current
4.5 VIN = VIL or VIH,
IOL = 24mA
5.5 VIN = VIL or VIH,
IOL = 24mA(4)
5.5 VI = VCC, GND
0.36 0.44
0.36 0.44
±0.1 ±1.0
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
Output Current(5)
Maximum Quiescent
Supply Current
5.5 VI = VCC − 2.1V
0.6
5.5 VOLD = 1.65V Max.
5.5 VOHD = 3.85V Min.
5.5 VIN = VCC or GND
4.0
1.5
75
−75
40.0
IOZT Maximum I/O
Leakage Current
5.5 VI (OE) = VIL, VIH;
VI = VCC, GND;
VO = VCC, GND
±0.3
±3.0
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
Units
V
V
V
V
µA
mA
mA
mA
µA
µA
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
5
www.fairchildsemi.com
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