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A25P020 PDF Datasheet - Serial Flash Memory - AMIC

Part Number A25P020
Description Serial Flash Memory
Manufacturers AMIC 
Logo AMIC Logo 
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A25P020 datasheet, circuit
A25P020 Series
Preliminary
2Mbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
Document Title
2Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors
Revision History
Rev. No.
0.0
0.1
0.2
History
Initial issue
Change supply voltage from “2.5V~3.6V to “2.3V~3.6V
Table 14. AC Characteristics (2.3V~3.6V): Update tPP, tSE, tBE, tCE values
Change 8-pin USON(2*3mm) package outline dimensions
Modify 8-pin USON(2*3mm) package outline dimensions
Issue Date
January 10, 2014
June 25, 2014
Remark
Preliminary
November 14, 2014
PRELIMINARY (November, 2014, Version 0.2)
AMIC Technology Corp.

1 page

A25P020 pdf, schematic
A25P020 Series
Preliminary
2Mbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
FEATURES
„ Family of Serial Flash Memories
- A25P020: 2M-bit /256K-byte
„ Flexible Sector Architecture with 4KB sectors
- Sector Erase (4K-bytes) in 200ms (typical)
- Block Erase (64K-bytes) in 0.5s (typical)
„ Page Program (up to 256 Bytes) in 0.8ms (typical)
„ 2.3V to 3.6V Single Supply Voltage
„ SPI Bus Compatible Serial Interface
„ 100MHz Clock Rate (maximum)
„ Advanced Protection Features
- Software and Hardware Write-Protect
- Top/Bottom, Block/Sector Array Protection
„ Electronic Signatures
- JEDEC Standard Two-Byte Signature
A25P020: (3012h)
- RES Instruction, One-Byte, Signature, for backward
compatibility
A25P020 (11h)
„ Package options
- 8-pin SOP (150/209mil), 8-pin DIP (300mil), 8-pin USON
(2*3mm) and 8-pin WSON (6*5mm)
- All Pb-free (Lead-free) products are RoHS2.0 compliant
GENERAL DESCRIPTION
The A25P020 is 2M bit Serial Flash Memory, with advanced
write protection mechanisms, accessed by a high speed
SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The memory is organized as 4 blocks, each containing 16
sectors. Each sector is composed of 16 pages. Each page is
256 bytes wide. Thus, the whole memory can be viewed as
consisting of 1024 pages, or 262,144 bytes.
The whole memory can be erased using the Chip Erase
instruction, a block at a time, using Block Erase instruction, or a
sector at a time, using the Sector Erase instruction.
Pin Configurations
„ SOP8 Connections
„ DIP8 Connections
„ USON8/WSON8 Connections
A25P020
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
A25P020
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
A25P020
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
PRELIMINARY (November, 2014, Version 0.2)
1
AMIC Technology Corp.

2 Page

A25P020 equivalent
SPI MODES
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
A25P020 Series
falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)Æ Mode 0
– C remains at 1 for (CPOL=1, CPHA=1)Æ Mode 3
Figure 1. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA)
= (0, 0) or (1, 1)
SDO
SDI
SCK
Bus Master
(ST6, ST7, ST9,
ST10, Other)
CS3 CS2 CS1
C DO DIO
SPI Memory
Device
S W HOLD
C DO DIO
SPI Memory
Device
S W HOLD
C DO DIO
SPI Memory
Device
S W HOLD
Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL CPHA
Mode 0 0
0C
Mode 3 1
1C
DIO
DO
MSB
MSB
PRELIMINARY (November, 2014, Version 0.2)
4
AMIC Technology Corp.

5 Page

A25P020 diode, scr
A25P020 MEMORY ORGANIZATION
The memory is organized as:
„ 262,144 bytes (8 bits each)
„ 4 64-Kbytes blocks
„ 64 4-Kbytes sectors
„ 1024 pages (256 bytes each).
Table 2. Memory Organization
A25P020 Address Table
Block
Sector
63
3
48
47
2
32
31
1
16
15
3
0
2
1
0
A25P020 Series
Each page can be individually programmed (bits are
programmed from 1 to 0). The device is Sector, Block, or Chip
Erasable (bits are erased from 0 to 1) but not Page Erasable.
3F000h
Address Range
3FFFFh
30000h
2F000h
30FFFh
2FFFFh
20000h
1F000h
20FFFh
1FFFFh
10000h
0F000h
03000h
02000h
01000h
00000h
10FFFh
0FFFFh
03FFFh
02FFFh
01FFFh
00FFFh
PRELIMINARY (November, 2014, Version 0.2)
8
AMIC Technology Corp.

9 Page

A25P020 transistor, igbt
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits
inside the chosen sector. Before it can be accepted, a Write
Enable (WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip
Select ( S ) Low, followed by the instruction code on Serial
Data Input (DIO). Chip Select ( S ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 13. Chip Select
( S ) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Sector Erase
Figure 13. Sector Erase (SE) Instruction Sequence
A25P020 Series
instruction is not executed. As soon as Chip Select ( S ) is
driven High, the self-timed Sector Erase cycle (whose
duration is tSE) is initiated. While the Sector Erase cycle is in
progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is
protected by the Sector/Block Protect (SEC, TB, BP2, BP1,
BP0) bits (see table 1 and table 2.) is not executed.
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction
24-Bit Address
DIO 23 22 21 3 2 1 0
MSB
Note: Address bits A23 to A18 are Don’t Care, for A25P020.
PRELIMINARY (November, 2014, Version 0.2)
20
AMIC Technology Corp.

21 Page





Information Total 30 Pages
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