A25L020C Series
2Mbit 3V Serial Flash Memory with 100MHz Uniform 4KB Sectors
Document Title
2Mbit 3V Serial Flash Memory with 100MHz Uniform 4KB Sectors
Revision History
Rev. No.
0.0
1.0
1.1
1.2
1.3
History
Initial issue
First version release
P.6: Add small sector protect function
Change 8-pin USON(2*3mm) package outline dimensions
P.1: Add “AEC-Q100 Grade 3 Certification” in FEATURES
Add automotive grade (-AF):
P.31: Add TA=-40°C~+125°C for –AF grade on Table 9
P.34: Add fC (Clock Frequency for the following instructions) Characteristic
for –AF grade on Table 15
P.37: Add –AF grade Part Numbering Scheme
P.38: Add –AF grade Ordering Information
Issue Date
April 01, 2011
April 18, 2011
November 21, 2012
November 14, 2014
December 1, 2014
Remark
Preliminary
Final
(December, 2014, Version 1.3)
AMIC Technology Corp.
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SPI MODES
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
A25L020C Series
falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)Æ Mode 0
– C remains at 1 for (CPOL=1, CPHA=1)Æ Mode 3
Figure 1. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA)
= (0, 0) or (1, 1)
SDO
SDI
SCK
Bus Master
(ST6, ST7, ST9,
ST10, Other)
CS3 CS2 CS1
C DO DIO
SPI Memory
Device
S W HOLD
C DO DIO
SPI Memory
Device
S W HOLD
C DO DIO
SPI Memory
Device
S W HOLD
Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL CPHA
Mode 0 0
0C
Mode 3 1
1C
DIO
DO
MSB
MSB
(December, 2014, Version 1.3)
4 AMIC Technology Corp.

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