|
|
PDF SN74LS160A Data sheet ( Hoja de datos )
| Número de pieza | SN74LS160A | |
| Descripción | BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SN74LS160A (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
SN74LS160A
BCD DECADE COUNTERS/
4-BIT BINARY COUNTERS
The LS160A/161A /162A /163A are high-speed 4-bit synchronous
counters. They are edge-triggered, synchronously presettable, and
cascadable MSI building blocks for counting, memory addressing,
frequency division and other applications. The LS160A and LS162A
count modulo 10 (BCD). The LS161A and LS163A count modulo 16
(binary).
The LS160A and LS161A have an asynchronous Master Reset
(Clear) input that overrides, and is independent of, the clock and all
other control inputs. The LS162A and LS163A have a Synchronous
Reset (Clear) input that overrides all other control inputs, but is active
only during the rising clock edge.
Asynchronous Reset
Synchronous Reset
BCD (Modulo 10)
LS160A
LS162A
Binary (Modulo 16)
LS161A
LS163A
• Synchronous Counting and Loading
• Two Count Enable Inputs for High Speed Synchronous Expansion
• Terminal Count Fully Decoded
• Edge-Triggered Operation
• Typical Count Rate of 35 MHz
• ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC TC Q0 Q1 Q2 Q3 CET PE
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts (Connection
Diagram) as the Dual In-Line Pack-
age.
1234
*R CP P0 P1
56 78
P2 P3 CEP GND
*MR for LS160A and LS161A
*SR for LS162A and LS163A
PIN NAMES
LOADING (Note a)
HIGH
LOW
PE
P0 −P3
CEP
CET
CP
MR
SR
Q0 −Q3
TC
Parallel Enable (Active LOW) Input
Parallel Inputs
Count Enable Parallel Input
Count Enable Trickle Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Synchronous Reset (Active LOW) Input
Parallel Outputs (Note b)
Terminal Count Output (Note b)
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
10 U.L.
10 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 7
1
http://onsemi.com
BCD DECADE COUNTERS/
4-BIT BINARY COUNTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
934 56
PE P0 P1 P2 P3
7 CEP
10 CET
TC 15
2 CP
*R Q0 Q1 Q2 Q3
1 14 13 12 11
VCC = PIN 16
GND = PIN 8
*MR for LS160A and LS161A
*SR for LS162A and LS163A
Publication Order Number:
MC74HC14A/D
1 page  
SN74LS160A
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the clock transition from LOW to HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the
correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
tW(H)
tW(L)
CP 1.3 V
tPHL
1.3 V
tPLH
Other conditions:
PE = MR (SR) = H
CEP = CET = H
Q 1.3 V
1.3 V
Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width
MR 1.3 V
CP
Q0 V Q1 V Q2 V Q3
tW
tPHL
trec
1.3 V
Other conditions:
PE = L
P0 = P1 = P2 = P3 = H
1.3 V
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
http://onsemi.com
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SN74LS160A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SN74LS160A | SYNCHRONOUS 4-BIT COUNTERS |  Texas Instruments |
| SN74LS160A | BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS |  Motorola Semiconductors |
| SN74LS160A | BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |