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PDF MT9V125 Data sheet ( Hoja de datos )
| Número de pieza | MT9V125 | |
| Descripción | 1/4-Inch System-On-A-Chip (SOC) VGA NTSC and PAL CMOS Digital Image Sensor | |
| Fabricantes | ON Semiconductor | |
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MT9V125: SOC VGA Digital Image Sensor
Features
1/4-Inch System-On-A-Chip (SOC) VGA
NTSC and PAL CMOS Digital Image Sensor
MT9V125 Datasheet, Rev. W
For the latest datasheet revision, please visit www.onsemi.com
Features
• System-on-a-chip (SOC)—completely integrated
camera system
• NTSC and PAL (true two field) analog composite
video output
• Low power, interlaced scan CMOS image sensor
• ITU-R BT.656 parallel output (8-bit, interlaced)
• Serial LVDS data output
• Supports use of external devices for addition of
custom overlay graphics
• Superior low-light performance
• On-chip image flow processor (IFP) performs
sophisticated processing
• Color recovery and correction, sharpening, gamma,
lens shading correction, and on-the-fly defect
correction
• Automatic Features:
Auto exposure (AE), auto white balance (AWB), auto
black reference (ABR), auto flicker avoidance, auto
color saturation, and auto defect identification and
correction
• Simple two-wire serial programming interface
Applications
• Automotive
– Rear view camera
– Side mirror replacement
– Blind spot view
– Occupant monitoring
• Security cameras
• Consumer video products
Data Sheet Applicable To
Silicon Revision: Rev4
Table 1:
Key Performance Parameters
Parameter
Optical format
Active imager size
Active pixels
NTSC output
PAL output
Pixel size
Color filter array
Shutter type
Maximum data rate/
master clock
Frame rate (VGA 640H x 480V)
Integration time
ADC resolution
Responsivity
Pixel dynamic range
SNRMAX
I/O digital
Supply voltage Core digital
Analog
Power
consumption1
Operating
Standby
Operating temperature
Package
Typical Value
1/4-inch (4:3)
3.63 mm (H) x 2.78 mm (V)
4.57 mm diagonal
640H x 480V
720H x 486V
720H x 576V
5.6 m x 5.6 m
RGB paired Bayer pattern
Electronic rolling shutter
(ERS)
13.5 Mp/s
27 MHz
30 fps at 27 MHz (NTSC)
25 fps at 27 MHz (PAL)
16 μs–33 ms (NTSC)
16 μs–40 ms (PAL)
10-bit, on-chip
5 V/lux-sec (550nm)
70 dB
39 dB
2.5–3.1 V
(2.8 V nominal)
2.5–3.1 V
(2.8 V nominal)
2.5–3.1 V
(2.8 V nominal)
320 mW
0.56 mW
–40°C to +85°C (functional
to +105°C)
52-Ball iBGA
Notes: 1. Measured at 2.8 V, 30 fps, 25°C
MT9V125_DS Rev.. W 6/15 EN
1 ©Semiconductor Components Industries, LLC 2015,
1 page  
MT9V125: SOC VGA Digital Image Sensor
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
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Table 9:
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Table 14:
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Table 16:
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Table 18:
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Table 25:
Table 26:
Table 27:
Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Readout Mode Register Settings – DOUT Not Qualified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
MT9V125 Readout Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Readout Mode Register Settings – DOUT Qualified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Register Address Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Blanking Minimum Values (in sensor stand-alone mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
LVDS Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Serial Output Data Timing Values (for EXTCLK = 27 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Field, Vertical Blanking, EAV, and SAV States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Field, Vertical Blanking, EAV, and SAV States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Parallel Input Data Timing Values Using DIN_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Parallel Input Data Timing Values Using EXTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
STANDBY Effect on the Output State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Signal State During Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Output Data Ordering in DOUT RGB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Output Data Ordering in Sensor Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Data Ordering in LVDS Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Video DAC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Digital I/O Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
NTSC Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Two-Wire Interface ID Address Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
MT9V125 Rev4 Imager Sensor Core Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
MT9V125_DS Rev.. W 6/15 EN
5 ©Semiconductor Components Industries, LLC,2015.
5 Page 
MT9V125: SOC VGA Digital Image Sensor
Detailed Architecture Overview
Detailed Architecture Overview
Sensor Core
The sensor consists of a pixel array of 695 x 512, an analog readout chain, a 10-bit ADC
with programmable gain and black offset, and timing and control as illustrated in
Figure 5.
Figure 5: Sensor Core Block Diagram
Active Pixel
Sensor (APS)
Array
Control Register
Timing and Control
Communication
Bus
to IFP
Clock
Sync
Signals
Analog Processing
ADC
10-Bit Data
to IFP
Pixel Array Structure
The sensor core pixel array is configured as 695 columns by 512 rows, as shown in
Figure 6. The first 42 columns and the first 13 rows of pixels are optically black, and can
be used to monitor the black level. The last four columns and the last row of pixels are
also optically black.
Figure 6: Pixel Array Description
Pixel logical address = (0, 0)
13 black rows
8 active border rows
Active paired Bayer pixel array
640 x 480
no horizontal/vertical flip
Pixel logical address = (694, 511)
8 + 2 active border rows
1 black row
(not to scale)
MT9V125_DS Rev.. W 6/15 EN
11
©Semiconductor Components Industries, LLC,2015.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT9V125.PDF ] | |
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