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PDF IZE4442 Data sheet ( Hoja de datos )
| Número de pieza | IZE4442 | |
| Descripción | INTELLIGENT 256-BYTE EEPROM | |
| Fabricantes | Integral | |
| Logotipo |  |
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IZE4442
INTELLIGENT 256-BYTE EEPROM WITH WRITE PROTECT FUNCTION
AND PROGRAMMABLE SECURITY CODE (PSC)
Features
• 256 x 8-bit EEPROM organization
• Byte-wise addressing
• Irreversible byte-wise write protection of lowest
• 32 addresses (Byte 0...31)
• 32 x 1-bit organization of protection memory
• Two-wire link protocol
• End of processing indicated at data output
• Answer-to-Reset ace. to ISO standard 7816-3
• Programming time 2.5 ms per byte for both erasing
• and writing
• Minimum of 104 write/erase cycles1)
• Data retention for minimum of ten years1)
• Contact configuration and serial interface in accordance
• with ISO standard 7816 (synchronous transmission)
Additional Feature of IZE4442
Data can only be changed after entry of the correct 3-byte programmable security code (security memory)
Type
Ordering Code
Package
IZE4442 M2.2
on request
Wire-Bonded Module M2.2
IZE4442 C
on request
Chip
IZE4442 M2.2
on request
Wire-Bonded Module M2.2
IZE4442 C
on request
Chip
1) Values are temperature dependent, for further information please refer to your sales office.
Pin Configuration(top view)
(Card Contacts)Pin Definitions and Functions
Card Contact
Symbol
Function
C1
VCC
Supply voltage
C2 RST
Reset
C3 CLK Clock input
C4
N.C.
Not connected
C5 GND
Ground
C6
N.C.
Not connected
C7 I/O Bi-directional data line
(open drain)
C8
N.C.
Not connected
IZE4442 comes as a M2.2 wire-bonded module for embedding in plastic cards or as a die for customer
packaging.
1
1 page  
IZE4442
In this mode the 1C processes internally. The 1C has to be clocked continuously until I/O, which was
switched to level L after the first falling edge of CLK, is set to high impedance level Z. Any start and stop
condition is discarded during this mode.
Note: The RST line is low during the modes mentioned above. If RST is set to high during the CLK low level
any operation is aborted and I/O is switched to high impedance Z (Break).
Figure 3 Operational Modes
Commands
Command Format
Each command consists of three bytes:
MSB Control LSB
MSB
Address
LSB
MSB Data
LSB
B7 B6 B5 B4 B3 B2 B1 B0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Beginning with the control byte LSB is transmitted first.
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IZE4442
32 Data Byte 32 (D7...D0)
-
31 Data Byte 31 (D7...D0) Protection Bit 31 (D31)
:
:
:
-
-
3
Data Byte 3 (D7...D0)
Protection Bit 3 (D3) Reference Data Byte 3 (07...D0)
2
Data Byte 2 (D7...D0)
Protection Bit 2 (D2) Reference Data Byte 2 (D7...D0)
1
Data Byte 1 (D7...D0)
Protection Bit 1 (D1) Reference Data Byte 1 (D7...D0)
0
Data Byte 0 (D7...D0)
Protection Bit 0 (D0) Error Counter (0,0,0,0,0,D2,D1,D0)
Command: READ SECURITY MEMORY
Control
Address
B7 B6 B5 B4 B3 B2 B1 BO A7...AO
Binary
0 0 1 1 0 0 0 1 No effect
Hexadecimal
31H
No effect
Data
D7...DO
No effect
No effect
Figure 9
Read Security Memory
2.3.6 Update Security Memory
Regarding the reference data bytes this command will only be executed if a PSC has been successfully
verified before. Otherwise only each bit of the error counter (Address 0) can be written from "1" to "0". The
execution times and the required clock pulses are the same as described under UPDATE MAIN MEMORY.
Command: UPDATE SECURITY MEMORY
Control
Address
Data
B7 B6 B5 B4 B3 B2 B1 BO A7...A0
D7...D0
Binary
0 0 1 1 1 0 0 1 Address Input data
Hexadecimal
39H
00H...03H Input data
2.3.7 Compare Verification Data
11
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet IZE4442.PDF ] | |
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