PDF ATUC128D3 Data sheet ( Hoja de datos )

Número de pieza	ATUC128D3
Descripción	32-bit AVR Microcontroller
Fabricantes	ATMEL Corporation
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No Preview Available ! Features • High Performance, Low Power 32-bit AVR® Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instructions – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performance • Up to 61 DMIPS Running at 48MHz from Flash (1 Flash Wait State) • Up to 34 DMIPS Running at 24MHz from Flash (0 Flash Wait State) • Multi-Hierarchy Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 7 Peripheral DMA Channels Improve Speed for Peripheral Communication • Internal High-Speed Flash – 128Kbytes, and 64Kbytes Versions – Single-Cycle Access up to 24MHz – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area • Internal High-Speed SRAM, Single-Cycle Access at Full Speed – 16Kbytes • Interrupt Controller (INTC) – Autovectored Low Latency Interrupt Service with Programmable Priority • External Interrupt Controller (EIC) • System Functions – Power and Clock Manager – SleepWalking™ Power Saving Control – Internal System RC Oscillator (RCSYS) – 32 KHz Oscillator – Clock Failure Detection – One Multipurpose Oscillator and two Phase Locked Loop (PLL) • Windowed Watchdog Timer (WDT) • Asynchronous Timer (AST) with Real-Time Clock Capability – Counter or Calendar Mode Supported • Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency • Universal Serial Bus (USB) – Device 2.0 full speed and low speed – Flexible End-Point Configuration and Management – On-chip Transceivers Including Pull-Ups • Three 16-bit Timer/Counter (TC) Channels – External Clock Inputs, PWM, Capture and Various Counting Capabilities • 7 PWM Channels (PWMA) – 12-bit PWM up to 150MHz Source Clock • Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Independent Baudrate Generator, Support for SPI – Support for Hardware Handshaking • One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals – Up to 15 SPI Slaves can be Addressed 32-bit AVR® Microcontroller ATUC128D3 ATUC64D3 ATUC128D4 ATUC64D4 Summary 32133D–11/2011 1 page UC3D 2. Overview 2.1 Block Diagram Figure 2-1. Block Diagram TCK TDO TDI TMS DATAOUT RESET_N JTAG INTERFACE aWire NEXUS CLASS 2+ OCD UC CPU INSTR INTERFACE DATA INTERFACE LOCAL BUS INTERFACE LOCAL BUS 16KB SRAM DP DM VBUS USB FS CONTROLLER MM MS M HIGH SPEED BUS MATRIX S S SM CONFIGURATION REGISTERS BUS HSB-PB BRIDGE B HSB-PB BRIDGE A PERIPHERAL DMA CONTROLLER POWER MANAGER CLOCK PA PB CONTROLLER SLEEP CONTROLLER RESET CONTROLLER GCLK[2..0] RCSYS XIN32 XOUT32 XIN0 XOUT0 RC120M OSC32K OSC0 PLL0 PLL1 BOD EXTINT[8..1] NMI SYSTEM CONTROL INTERFACE INTERRUPT CONTROLLER EXTERNAL INTERRUPT CONTROLLER ASYNCHRONOUS TIMER WATCHDOG TIMER FREQUENCY METER PWM[6..0] PWM CONTROLLER USART0 USART1 USART2 SPI TWI MASTER TWI SLAVE 8-CHANNEL ADC INTERFACE INTER-IC SOUND CONTROLLER CAPACITIVE TOUCH SENSOR CONTROLLER TIMER/COUNTER GLUE LOGIC CONTROLLER 64/128KB FLASH RXD TXD CLK RTS, CTS SCK MISO, MOSI NPCS[3..0] TWCK TWD TWCK TWD AD[7..0] ADVREF DOUT DIN FSYNC CLK MCLK CSA[24..0] CSB[24..0] A[2..0] B[2..0] CLK[2..0] OUT[3:0] IN[15..0] PA PB 32133D–11/2011 5 5 Page UC3D 3.2.4 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-4. Oscillator Pinout 48-pin Package 30 31 22 23 64-pin Package 39 40 30 31 Pin PA18 PA19 PA11 PA12 Oscillator Function XIN0 XOUT0 XIN32 XOUT32 3.2.5 Other Functions The functions listed in Table 3-5 are not mapped to the normal GPIO functions.The aWire DATA pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be active after the aWire is enabled and the 2-pin mode command has been sent. Table 3-5. Other Functions 48-Pin Package 47 2 64-Pin Package 63 2 Pin RESET_N PB12 Function aWire DATA aWire DATAOUT 32133D–11/2011 11 11 Page

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