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What is PH6030L?

This electronic component, produced by the manufacturer "NXP Semiconductors", performs the same function as "N-channel TrenchMOS logic level FET".


PH6030L Datasheet PDF - NXP Semiconductors

Part Number PH6030L
Description N-channel TrenchMOS logic level FET
Manufacturers NXP Semiconductors 
Logo NXP Semiconductors Logo 


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PH6030L
N-channel TrenchMOS logic level FET
Rev. 01 — 29 July 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features and benefits
„ Lead-free package
„ Logic level compatibile
„ Optimized for use in DC-to-DC
converters
„ Very low switching and conduction
losses
1.3 Applications
„ DC-to-DC convertors
„ Notebook computers
„ Switched-mode power supplies
„ Voltage regulators
1.4 Quick reference data
Table 1. Quick reference
Symbol
VDS
ID
Parameter
drain-source voltage
drain current
Conditions
Tj 25 °C; Tj 150 °C
Tmb = 25 °C; VGS = 10 V;
see Figure 1; see Figure 3
Dynamic characteristics
QGD
gate-drain charge VGS = 4.5 V; ID = 25 A;
VDS = 12 V; see Figure 11;
see Figure 12
Static characteristics
RDSon
drain-source
on-state resistance
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 9; see
Figure 10
Min Typ Max Unit
- - 30 V
- - 76.7 A
- 3.1 - nC
-
4.7 6
m

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PH6030L equivalent
NXP Semiconductors
PH6030L
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol
Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source
breakdown voltage
gate-source threshold
voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 1 mA; VDS = VGS; Tj = -55 °C; see
Figure 7
ID = 1 mA; VDS = VGS; Tj = 150 °C; see
Figure 7
ID = 1 mA; VDS = VGS; Tj = 25 °C; see
Figure 7; see Figure 8
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 25 A; Tj = 150 °C; see
Figure 9
VGS = 4.5 V; ID = 25 A; Tj = 25 °C; see
Figure 9; see Figure 10
VGS = 10 V; ID = 25 A; Tj = 25 °C; see
Figure 9; see Figure 10
RG gate resistance
Dynamic characteristics
f = 1 MHz
QG(tot)
total gate charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V; see
Figure 11; see Figure 12
ID = 0 A; VDS = 0 V; VGS = 4.5 V; see
Figure 11
QGS
QGD
QGS1
gate-source charge
gate-drain charge
pre-threshold
gate-source charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V; see
Figure 12; see Figure 12
QGS2
post-threshold
gate-source charge
VGS(pl)
gate-source plateau ID = 25 A; VDS = 12 V; see Figure 11; see
voltage
Figure 12
Ciss
Coss
Crss
input capacitance
output capacitance
reverse transfer
capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 13
VDS = 0 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 13
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 13
Min Typ Max Unit
27 -
30 -
--
-V
-V
2.6 V
0.8 -
-
V
1.3 1.7
2.15 V
- - 1 µA
--
100 µA
--
100 nA
--
100 nA
- 8.5 10.6 m
-
7.3 9.7
m
- 4.7 6
m
- 1.75 -
- 15.2 -
- 14 -
- 8.5 -
- 3.1 -
- 4.1 -
- 4.4 -
- 3.5 -
- 2260 -
- 2540 -
- 460 -
- 210 -
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
pF
PH6030L_1
Product data sheet
Rev. 01 — 29 July 2008
© NXP B.V. 2008. All rights reserved.
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1. N-channel TrenchMOS logic level FET

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