IN1363 Datasheet PDF - IK Semiconductor
Part Number | IN1363 | |
Description | CMOS LIS of Real Time Watch | |
Manufacturers | IK Semiconductor | |
Logo | ||
There is a preview and IN1363 download ( pdf file ) link at the bottom of this page. Total 30 Pages |
Preview 1 page No Preview Available ! TECHNICAL DATA
CMOS LIS of Real Time Watch with Serial Interface
IN1363
FEATURES
Count of seconds, minutes, hours, week days, date, months and
years with consideration of leap years (until 2100);
400 kHz, double wire serial interface;
Programmed orthogonal output signal;
Function programming of alarm, timer and interruption;
Automatic determination of the supply voltage drop;
Consumption current of less, than 450 nA with supply of 2V with the
operating oscillator;
Operating temperature range: -40С – 85С.
SOP- 8
MSOP-8
ТА = - 40 ... + 85 С
for all packages
ORDERING INFORMATION
Device
IN1363DT
IN1363D
IN1363MDT
IN1363MD
Operating
Temperature Range
ТА = - 40 ... + 85 С
Package
SOP-8
SOP-8
MSOP-8
MSOP-8
Shipping
Tape & Reel
Tube
Tape & Reel
Tube
DESCRIPTION
Microcircuit IN1363 is essentially the complete binary-decimal digital watch with calendar, alarm, timer and
possesses low power consumption. Addresses and data are transferred in series via the double wire bi-
directional bus. The microcircuit is intended for count of real time in hours, minutes and seconds, count of
week days, date, month and year. The last day of the month is automatically adjusted for the months with
fewer, than 31 days, including correction for the leap year. The watch functions in the 24 hour mode. The
microcircuit IN1363 has the built-in power control circuit, which determines the power level < 1V and forms
the bit, signaling, that information about the real time may not be correct.
1 Aug 2012, ver.05
|
|
IN1363
DYNAMIC CHARACTERISTICS
(ТА = –40...+ 85С, VCC = 4,5 – 5,5 V are listed in the table)
Characteristics
Symbol
Test Condition Min Max Unit
Cycle frequency SCL
Time of bus vacant condition between the
conditions STOP and START
Hold time (repeated) of the condition START
fSCL
tBUF
tHD:STA1)
– 0 400 kHz
–
4,7 –
us
–
0,6 –
us
Low condition duration of the cycle pulse SCL
tLOW
–
1,3 –
us
High condition duration of the cycle pulse SCL
Presetting time for the repeated condition
START
Data hold time
Data presetting time
Rise time for signals SDA and SCL
Drop time for signals SDA and SCL
Presetting time for the condition STOP
Total capacitance load on each bus line
Capacity input/output
Load capacitance of the quartz resonator
tHIGH
tSU:STA
tHD:DAT2)
tSU:DAT
tR
tF
tSU:STO
CB
CI/O
СLX
–
0,6 –
us
–
0,6 –
us
–
0–
us
–
100 –
ns
– – 300 ns
– – 300 ns
–
0,6 –
us
– – 400 pF
– 10 10 pF
– 12,5 12,5 pF
1) After this time interval the first cycle signal is formed;
2) The device should internally ensure the hold time, at least, 300 nsec for the signal SDA (relative to VIHMIN
of the signal SCL) in order to overlap the indeterminacy area of the signal SCL drop front
Maximum value tHD:DAT should be definite in that case, if the device does not increase duration of the
low condition (tLOW) of the signal SCL
5 Aug 2012, ver.05
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IN1363 electronic component. |
Information | Total 30 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ IN1363.PDF Datasheet ] |
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