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PDF LVDS Data sheet ( Hoja de datos )
| Número de pieza | LVDS | |
| Descripción | Low-Voltage Differential Signaling | |
| Fabricantes | Agilent Technologies | |
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Low-Voltage Differential Signaling (LVDS)
Application Note 1382-6
by Stephen Kempainen, National Semiconductor
Who Should Read This
Application Note?
Digital designers utilizing low-
voltage differential signaling
(LVDS) for high-speed data
transmissiom.
LVDS Provides Higher Bit Rates,
Lower Power, and Improved
Noise Performance
Due to the Internet’s tremendous
growth, data transfers are
increasing dramatically in all
areas of communications. In addi-
tion, data streams for digital
video, HDTV, and color graphics
are requiring higher and higher
bandwidth. The digital communi-
cations deluge is the driving force
for high-speed interconnects
between chips, functional boards,
and systems. The data may be
digital, but it is analog Low-
Voltage Differential Signaling
(LVDS) that designers are choos-
ing to drive these high-speed
transmission lines. LVDS’s proven
speed, low power, noise control,
and cost advantages are popular
in point-to-point applications for
telecommunications, data
communications, and displays.
LVDS uses high-speed analog
circuit techniques to provide
multi-gigabit data transfers on
copper interconnects.
Wherever you need high-speed
data transfer (100 Mb/s and
higher), LVDS offers a solution.
There are many applications in
many market segments that use
LVDS for data transmission.
These include:
• stackable hubs for data
communications
• wireless base stations
and ATM switches in
telecommunications
• flat-panel displays and servers
in the computer market
• peripherals like printers and
digital copy machines
• high-resolution displays in
industrial applications
• flat-panel displays in the
automotive market
In these applications, high-speed
data moves within and between
systems. Moving data within a
system (intrasystem data trans-
fer) is the main use for LVDS
solutions today. Moving informa-
tion between systems (intersys-
tem data transfer) requires stan-
dard communication protocols
such as IEEE 1394, Fibre
Channel, and Gigabit Ethernet.
Since the hardware and software
overhead for intersystem proto-
cols is too expensive to use for
intrasystem data transfers, a sim-
ple and low-cost LVDS link is an
attractive alternative. Thus, LVDS
solutions move information on a
board, between boards, modules,
shelves, and racks, or box-to-box.
The transmission media can be
copper cables or printed circuit
board (PCB) traces. In the future,
LVDS will also carry protocols for
inter-system communication.
Table of Contents
LVDS Provides Higher Bit Rates,
Lower Power, and Improved
Noise Performance . . . . . . . . . . . . . . . . . 1
Generic LVDS. . . . . . . . . . . . . . . . . . . . . . . 2
Multiple Technologies and
Supply Voltages . . . . . . . . . . . . . . . . . . . . 3
Gigabits at Milliwatts . . . . . . . . . . . . . . . 4
Flat Supply Current vs.
Operating Frequency . . . . . . . . . . . . . . . . 6
Low Electromagnetic Interference . . . . 7
Cost Benefits . . . . . . . . . . . . . . . . . . . . . . . 8
Many Channels per Chip . . . . . . . . . . . . . . 8
DC Balance for Longer Cables . . . . . . . . 9
Bus LVDS . . . . . . . . . . . . . . . . . . . . . . . . . 10
The Complexities of
Signal Integrity . . . . . . . . . . . . . . . . . . . . 11
Serializer/Deserializer Example . . . . . . . 11
LVDS in Low-Power Applications. . . . 12
Test and Evaluation Considerations . . 13
BER Eye Diagram . . . . . . . . . . . . . . . . . . 15
Recovered Clock Jitter . . . . . . . . . . . . . 16
ParBERT 81250 Simplifies
the Characterization and
Testing of LVDS Devices . . . . . . . . . . . . 17
81200 Provides the Tools
to Test LVDS. . . . . . . . . . . . . . . . . . . . . . . 18
Related Literatute . . . . . . . . . . . . . . . . . 19
Support, Services, and Assistance. . . 20
1 page  
Gigabits at Milliwatts (continued)
Besides giving tremendous
throughput, the chipset reduces
the interconnect width and pro-
vides other system benefits. The
cable and connector are smaller
and lower cost; the cable is more
flexible, and the connector has
fewer pins.
The beautiful eye pattern in
figure 4 is taken at the end of
a 5-meter cable between the
transmitter and receiver of the
OpenLDI chipset. The transmitter
drives a Pseudo Random Bit
Sequence through the cable, and
the receiver recovers the signal.
The markers show the bit width
to be 1.275 ns, indicating a data
rate of 784 Mb/s. Each of the 8
pairs carries this raw data rate,
resulting in an aggregate band-
width of almost 6.3 Gb/s. This
data rate includes overhead for
DC balance, so the actual payload
bandwidth is 5.38 Gb/s.
Figure 4. Eye pattern measured at the end
of a 5-meter cable between the transmitter
and receiver of the OpenLDI chipset.
5
5 Page 
The Complexities of Signal Integrity
Signal integrity in a heavily
loaded backplane is a very com-
plicated problem due to the many
impedance discontinuities inher-
ent in the backplane environ-
ment. The worst-case situation in
bus signaling occurs when a card
in the middle of the bus drives a
signal into the backplane and the
card in the adjacent slot looks to
receive the signal. The edge rate
from the driving card is very fast
as the signal leaves it and travels
down the backplane. The adjacent
cards see the fast edge propagate
into the signal stub. This fast edge
rate causes reflections on the
stub that can glitch through the
receiver threshold region. (The
most important factor for high-
speed performance in all bus
topologies is keeping each receiv-
er’s non-terminated stub very
short, minimizing reflections
from that stub.)
BLVDS uses the same basic
schematic as LVDS, but extends
LVDS’s point-to-point and simple
multidrop applications to true
multipoint busing functionality.
It does this by boosting the drive
current to 10 mA to drive double
terminations on heavily loaded
buses, and by providing driver
output impedance that matches
the line impedance to reduce
reflections from driver outputs.
One of the essential features
required in a multidrop bus is
the ability to insert cards into
the bus without powering it down.
The optimal hot-insertion capa-
bility is to insert cards without
stopping or disturbing the data
traffic on the bus. BLVDS sup-
ports this optimal hot-insertion
capability, as the signal glitch
caused by inserting the capacitive
load of the plug-in card occurs
equally on each of the differential
lines that have a low impedance
connection between them. There-
fore there is no change to the
differential signal.
Serializer/Deserializer Example
An application example of Bus
LVDS technology is the serializer/
deserializer chipset. The trans-
mitter serializes a 10-bit parallel
LVTTL interface into a single
BLVDS data channel, and also
embeds the clock in the serial
stream. The BLVDS receiver
recovers the clock and data to
deserialize them back into the
10-bit parallel interface.
This chipset distributes data over
a serial channel in multidrop dis-
tribution systems. One serializer
can drive many deserializers in
either of the multidrop configura-
tions shown in figure 7. Multi-
point application is also possible
with certain limitations due to
PLL lock time. The limitations
arise when a new driver begins
to drive the bus and all the
receivers must lock to that dri-
ver’s clock signal. In addition, the
chipset works in point-to-point
applications. The chipset sup-
ports TTL clock rates from 16 to
66 MHz. For example, the chipset
transfers a 660-Mb/s payload
over a 10-meter cable when the
10-bit interface operates with a
66-MHz clock.
The chipset’s waveform has a
10-bit payload surrounded by
two embedded clock bits. The
actual serial bit rate with a
40-MHz clock is 480 Mb/s, but
the throughput is 400 Mb/s. The
receiver uses the embedded
clock edges to lock onto the
inbound serial stream and to
align the data at the parallel out-
put. It provides greater system
benefits than other LVDS parts
by eliminating the cost of a cable
or PCB differential pair for the
clock signal.
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LVDS.PDF ] | |
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