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What is IN25AA040N?

This electronic component, produced by the manufacturer "Integral", performs the same function as "NONVOLATILE ELECTRICALLY ERASABLE PROM".


IN25AA040N Datasheet PDF - Integral

Part Number IN25AA040N
Description NONVOLATILE ELECTRICALLY ERASABLE PROM
Manufacturers Integral 
Logo Integral Logo 


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IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
NONVOLATILE ELECTRICALLY ERASABLE PROM WITH SERIAL
PERIPHERAL INTERFACE (SPI).
DESCRIPTION
The IN25АА020N/D are a 2K(256x8) serial Electrically Erasable PROM with SPI interface.
*The IN25АА040N/D are a 4K (512x8) serial Electrically Erasable PROM with SPI interface (SPI).
The ICs is purposed for reading, writing & nonvolatile data storage in electronic units with SPI interface. ICs
are realized in SO-8 (MS-012АA) and DIP-8 (MS-001BA)
FEATURES
- Data capacity, QINF:
for IN25АА020N, IN25АА020D
for IN25АА040N, IN25АА040D
2048 bit,
4096 bit;
- Maximum clock frequency, fC:
for 4,5 V UCC 5,5 V
for 2,5 V UCC 5,5 V
for 1,8 V UCC 5,5 V
- Maximum stand-by current, ICC:
for UCC = 5,5 V, UIL = 0 V, UIH = UCC
for UCC = 2,5 V, UIL = 0 V, UIH = UCC
3 MHz;
2 MHz;
1 MHz;
5,0 uA
1,0 uA;
- Maximum read current, IOCCR :
for UCC = 5,5 В, fC = 3,0 МГц, SO pin is not loaded .…1,0 mA,
for UCC = 2,5 В, fC = 2,0 МГц, SO pin is not loaded …..0,5 mA;
- Maximum write current, IOCCW :
for UCC = 5,5 V
5,0 mA;
for UCC = 2,5 V
3,0 mA;
- Byte & page (16 bytes) data write modes are available;
- Endurance NE/W, …...1000000 cycles;
- Write protection block protect none, 1/4, 1/2, or all of storage
array;
- Power on/off data protection circuitry;
- Supply voltage UCC 1,8 … 5,5 V;
- Temperature range -40 … +85°C.
- 100 years non-volatile data retention time
N SUFFIX
DIP
8
1 D SUFFIX
8 SOIC
1
Pin
Name
CS
SO
WP
GND
SI
SCK
HOLD
VCC
Function
Chip Select
Serial Data Output
Write protection
Ground
Serial Data Input
Clock Input
Hold input *
Power Supply
PIN FUNCTIONS
CS 01
SO 02
WP 03
GND 04
08 Vcc
07 HOLD
06 SCK
05 SI
Ver.00/11.07.2008
1 IN25AA020(040)-TSe.doc
1711616

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IN25AA040N equivalent
IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
Data read sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
Lower address byte
SI 0 0 0 0 A8 0 1 1 A7 6 5 4 3 2 1 A0
SO High-Z
Output data
7 6 5 43 2 1 0
There are six 8-bit instructions available for executing of read/write operation. The feature
of IN25AA040N, IN25AA040D with 4K capacity is that higher address byte (А8) is transmitted by
5th bit of data read/write instruction , for IN25AA020N, IN25AA020D with 2K capacity 5th bit of
instruction (A8) is ignored.
Enable/disable instructions а) “Write enable” - WREN & b) “Write disable” - WRDI
CS CS
SCK
01 2 3 4 5 6 7
SCK
01 2 3 4 5 6 7
SI 0 0 0 0 0 1 1
SI 0 0 0 0 0 1 10 0
SO High-Z
a)
High-Z
SO
b)
The powers up set ICs in the write disable state. For writing operation after power-up or
after an WRDI (write disable) instruction, WREN (write enable) instruction must be issued.
Any read/write operation can be executed on condition that CS =0 (enable signal) , high level on
CS pin switch IC to standby mode. Already intiated programming cycle will be comleted inde-
pendently from CS signal. A low to high transition on CS after a valid write sequence initiates an
internal write cycle.
Ver.00/11.07.2008
5 IN25AA020(040)-TSe.doc
1711616


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